A switching circuit arrangement (100) comprises a field effect transistor (40) and circuitry (50, 52, 54, 60, 62) for biasing the gate voltage of the field effect transistor (40), in particular forcing the gate voltage of the field effect transistor (40) under a certain threshold, in particular under a certain positive threshold level. In embodiments, reverse recovery as well as gate bounce are simultaneously mitigated. In one embodiment, the biasing circuitry comprises a biasing diode (52) connected in series to the gate (G) of the field effect transistor (40) to bias the gate voltage of the field effect transistor (40), as well as a clamping field effect transistor unit (62) connected between the gate (G) of the field effect transistor (40) and the source (S) of the field effect transistor (40) to force the gate voltage of the field effect transistor (40) under a certain threshold, in particular under a certain positive threshold level.