发明申请
- 专利标题: PLL Apparatus
- 专利标题(中): PLL装置
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申请号: US12225565申请日: 2007-03-20
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公开(公告)号: US20090146742A1公开(公告)日: 2009-06-11
- 发明人: Naoki Onishi , Shunichi Wakamatsu , Tsuyoshi Shiobara
- 申请人: Naoki Onishi , Shunichi Wakamatsu , Tsuyoshi Shiobara
- 优先权: JP2006-100614 20060331
- 国际申请: PCT/JP2007/057693 WO 20070320
- 主分类号: H03L7/14
- IPC分类号: H03L7/14
摘要:
It is an object of the present invention to provide a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble.As a concrete means for solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.
公开/授权文献
- US07755436B2 PLL apparatus 公开/授权日:2010-07-13
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