An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.