-
公开(公告)号：US07788435B2
公开(公告)日：2010-08-31
申请号：US11971775
申请日：2008-01-09
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.
摘要翻译： 用于多处理器计算机的中断重定向和聚合系统。 设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。 通过将多个中断通知组合成单个中断消息到处理器，可以提高处理效率。 对于多处理器计算机上的一些中断，例如那些信令完成分配给设备的输入/输出（I / O）操作），处理器的处理效率可能随处理器而异。 可以通过适当地聚合多个队列内和/或跨多个队列的中断消息来改善处理效率和整体计算机系统操作，其中中断基于他们所针对的哪个处理器进行排队。
-
公开(公告)号：US20090177829A1
公开(公告)日：2009-07-09
申请号：US11971775
申请日：2008-01-09
CPC分类号： G06F9/4812
摘要： An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.
摘要翻译： 用于多处理器计算机的中断重定向和聚合系统。 设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。 通过将多个中断通知组合成单个中断消息到处理器，可以提高处理效率。 对于多处理器计算机上的一些中断，例如那些信令完成分配给设备的输入/输出（I / O）操作），处理器的处理效率可能随处理器而异。 可以通过适当地聚合多个队列内和/或跨多个队列的中断消息来改善处理效率和整体计算机系统操作，其中中断基于他们所针对的哪个处理器进行排队。
-
公开(公告)号：US20090157935A1
公开(公告)日：2009-06-18
申请号：US12002442
申请日：2007-12-17
申请人： Bruce Worthington , Vinod Mamtani , Brian Railing
发明人： Bruce Worthington , Vinod Mamtani , Brian Railing
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.
摘要翻译： 用于多处理器计算机的高效中断系统。 设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。 这些设备配置有各自针对处理器的消息。 在接收到执行操作的命令时，该设备可以在该操作完成时接收用于中断处理器的优选消息的指示。 处理每个中断的效率和计算机的整体运行效率通过为计算机内的设备定义消息来增加，使得每个设备包含针对分布在处理器组之间的处理器的消息，每个组表示处理器接近 。 在选择消息的目标处理器时，选择处理器来跨处理器组和每个组内的处理器扩展处理。
-
公开(公告)号：US07783811B2
公开(公告)日：2010-08-24
申请号：US12002442
申请日：2007-12-17
申请人： Bruce Worthington , Vinod Mamtani , Brian Railing
发明人： Bruce Worthington , Vinod Mamtani , Brian Railing
CPC分类号： G06F13/24
摘要： An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.
摘要翻译： 用于多处理器计算机的高效中断系统。 设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。 这些设备配置有各自针对处理器的消息。 在接收到执行操作的命令时，该设备可以在该操作完成时接收用于中断处理器的优选消息的指示。 处理每个中断的效率和计算机的整体运行效率通过为计算机内的设备定义消息而增加，使得每个设备包含针对分布在处理器组之间的处理器的消息，每个组表示处理器接近 。 在选择消息的目标处理器时，选择处理器来跨处理器组和每个组内的处理器扩展处理。
-
-
-
搜索结果
4 条记录 (耗时 0.034 秒)
