发明申请
US20090189296A1 FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE
审中-公开
卷芯四边平板非引线包装结构及其制造方法和芯片包装结构
- 专利标题： FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE
- 专利标题（中）： 卷芯四边平板非引线包装结构及其制造方法和芯片包装结构
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申请号： US12275172申请日： 2008-11-20
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公开(公告)号： US20090189296A1公开(公告)日： 2009-07-30
- 发明人: Cheng-Ting Wu , Hung-Tsun Lin , Yu-Ren Chen , Chun-Ying Lin
- 申请人： Cheng-Ting Wu , Hung-Tsun Lin , Yu-Ren Chen , Chun-Ying Lin
- 申请人地址： TW Hsinchu
- 专利权人： CHIPMOS TECHNOLOGIES INC.
- 当前专利权人： CHIPMOS TECHNOLOGIES INC.
- 当前专利权人地址： TW Hsinchu
- 优先权： TW97103470 20080130; TW97103472 20080130; TW97105932 20080220
- 主分类号： H01L23/52
- IPC分类号： H01L23/52 ; H01L21/00
摘要：
A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.