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    FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE
    1.
    发明申请
    FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE 审中-公开
    卷芯四边平板非引线包装结构及其制造方法和芯片包装结构

    公开(公告)号：US20090189296A1

    公开(公告)日：2009-07-30

    申请号：US12275172

    申请日：2008-11-20

    申请人： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

    发明人： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

    IPC分类号： H01L23/52 ,  H01L21/00

    CPC分类号： H01L23/3114 ,  H01L23/49517 ,  H01L23/49822 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

    摘要翻译： 提供了一种倒装芯片四边形扁平无铅封装结构的制造方法。 首先在制造方法中设置具有多根引线的引线框架。 在引线框架上形成介电层，并使引线的顶表面和底表面露出。 在电介质层上形成包括多个焊盘的重分配层和连接焊盘和引线顶表面的多条导线。 形成阻焊层以覆盖再分布层，电介质层和引线，并露出焊盘的表面。 在阻焊层上形成粘接层。 提供具有多个凸块的芯片。 该芯片用粘合剂层粘附在阻焊层上，并且每个凸块与其中一个焊盘电连接。

    Chip package
    2.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US07932531B2

    公开(公告)日：2011-04-26

    申请号：US12506255

    申请日：2009-07-21

    申请人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

    发明人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

    IPC分类号： H01L33/00

    CPC分类号： H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

    摘要翻译： 芯片封装包括热增强板，围绕热增强板接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

    CHIP PACKAGE
    4.
    发明申请
    CHIP PACKAGE 有权
    芯片包装

    公开(公告)号：US20090321918A1

    公开(公告)日：2009-12-31

    申请号：US12506255

    申请日：2009-07-21

    申请人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

    发明人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

    IPC分类号： H01L23/498

    CPC分类号： H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

    摘要翻译： 芯片封装包括热增强板，围绕热增强板接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

    Method of fabricating quad flat non-leaded package
    9.
    发明授权
    Method of fabricating quad flat non-leaded package 有权
    制造四方扁平无铅封装的方法

    公开(公告)号：US07842550B2

    公开(公告)日：2010-11-30

    申请号：US12332362

    申请日：2008-12-11

    申请人： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

    发明人： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

    IPC分类号： H01L21/00

    CPC分类号： H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

    摘要翻译： 制造四边形扁平非引线封装的方法包括首先在牺牲层上形成图案化的导电层。 图案化导电层包括多个引线组。 许多芯片附着到牺牲层。 每个芯片都被其中一个引线组包围。 每个芯片电连接到一个引线组，并且在牺牲层上形成模制化合物以覆盖图案化的导电层和芯片。 然后将成型化合物和图案化导电层切割并切割，并且牺牲层被预切割以在牺牲层上形成多个凹部。 在模制化合物和图案化的导电层被切割并切割并且牺牲层被预切割之后，去除牺牲层。