发明申请
US20090194880A1 WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
有权
WAFER LEVEL CHIP SCALE包装及其制造工艺
- 专利标题： WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
- 专利标题（中）： WAFER LEVEL CHIP SCALE包装及其制造工艺
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申请号： US12023921申请日： 2008-01-31
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公开(公告)号： US20090194880A1公开(公告)日： 2009-08-06
- 发明人: Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
- 申请人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
- 申请人地址： BM Hamilton
- 专利权人： ALPHA & OMEGA SEMICONDUCTOR, LTD.
- 当前专利权人： ALPHA & OMEGA SEMICONDUCTOR, LTD.
- 当前专利权人地址： BM Hamilton
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L21/304
摘要：
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
公开/授权文献
- US07955893B2 Wafer level chip scale package and process of manufacture 公开/授权日：2011-06-07
信息查询
IPC分类:
