摘要:
The invention provides an anti-frozen processing apparatus and method used in a shrink fitting process of an inter component and outer component, which can reduce and eliminate the icy layer on the surface of low temperature inner component, and also can increase the productivity, improve the fitting quality and reduce the nitrogen consumption.
摘要:
Polymorphs of 3-chloro-4[(2R)-2-(4-chlorophenyl)-4-[(1R)-1-(4-cyanophenyl)ethyl]-1-piperazinyl]-benzonitrile are disclosed, as well as pharmaceutical compositions comprising said polymorphs, methods of using the polymorphs, and a process for preparing them.
摘要:
The present invention relates to pharmaceutical technical field, to melonine bisindole compounds, pharmaceutical compositions thereof, and preparation methods thereof. Specifically, the present invention relates to melonine bisindole compounds of Formula I, pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts thereof. The present invention further relates to method for preparing the melonine bisindole compounds of Formula I or pharmaceutically acceptable salts thereof, and the use of the melonine bisindole compounds of Formula I or pharmaceutically acceptable salts thereof in the manufacture of a medicament for the treatment or prophylaxis of cancers.
摘要:
A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.
摘要:
Wafer-level chip scale packaging of metal-oxide-semiconductor-field-effect-transistors (MOSFET's) provides protection and good solder-ability to a die backside by fabricating a plurality of power MOSFET devices with die contacts on a wafer that can later be cut into individual die. A plurality of contact pads is included on the wafer to provide connectivity to the die contacts. A layer which includes aluminum (Al) or zinc (Zn) is electrolessly plated on a backside of the wafer to form a metalized backside. The plating tank used in this step is not contaminated. The contact pads and metalized backside are plated with a layer of electroless nickel (Ni) followed by a layer of gold (Au). Solder balls are formed on each of the contact pads after their plating with nickel (Ni) and gold (Au). The wafer is diced to yield MOSFET wafer level chip-scale packages which provide protection and good solder-ability to the die backside.
摘要:
A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.
摘要:
A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
摘要:
A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
摘要:
A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.
摘要:
A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.