发明申请
US20090219044A1 Calibration technique for measuring gate resistance of power MOS gate device at wafer level
有权
用于在晶圆级测量功率MOS栅极器件的栅极电阻的校准技术
- 专利标题： Calibration technique for measuring gate resistance of power MOS gate device at wafer level
- 专利标题（中）： 用于在晶圆级测量功率MOS栅极器件的栅极电阻的校准技术
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申请号： US12454004申请日： 2009-05-11
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公开(公告)号： US20090219044A1公开(公告)日： 2009-09-03
- 发明人: Anup Bhalla , Sik K. Lui , Daniel Ng
- 申请人： Anup Bhalla , Sik K. Lui , Daniel Ng
- 专利权人： Alpha & Omega Semiconductor, LTD
- 当前专利权人： Alpha & Omega Semiconductor, LTD
- 主分类号： G01R31/26
- IPC分类号： G01R31/26 ; G01R31/02
摘要：
This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
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