发明申请
US20090258471A1 Application of Different Isolation Schemes for Logic and Embedded Memory
有权
不同隔离方案在逻辑和嵌入式存储器中的应用
- 专利标题: Application of Different Isolation Schemes for Logic and Embedded Memory
- 专利标题(中): 不同隔离方案在逻辑和嵌入式存储器中的应用
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申请号: US12489223申请日: 2009-06-22
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公开(公告)号: US20090258471A1公开(公告)日: 2009-10-15
- 发明人: Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
- 申请人: Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 主分类号: H01L21/8244
- IPC分类号: H01L21/8244 ; H01L21/762
摘要:
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.