-
公开(公告)号：US08470675B2
公开(公告)日：2013-06-25
申请号：US13274698
申请日：2011-10-17
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/823462
摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.
摘要翻译： 一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物 或LDMOS晶体管。 一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物， 另一栅极电介质层，并且保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。
-
公开(公告)号：US08426281B2
公开(公告)日：2013-04-23
申请号：US12961885
申请日：2010-12-07
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.
摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹
-
3.发明授权Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom 有权包括具有多个栅介质厚度的工艺和其集成电路的沟槽隔离公开(公告)号：US07888196B2
公开(公告)日：2011-02-15
申请号：US12345072
申请日：2008-12-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/76229 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness
摘要翻译： 一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管， 其中所述第一厚度<所述第二厚度。 提供具有半导体表面的衬底。 具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。 在包括第二区域的半导体表面上形成硬掩模层。 通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。 多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。 在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。 然后完成第一和第二区域中的MOS晶体管的制造。
-
4.发明申请METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW 审中-公开在应变CMOS流中积聚硅锗和碳掺杂硅的方法公开(公告)号：US20080283926A1
公开(公告)日：2008-11-20
申请号：US11750690
申请日：2007-05-18
申请人： Seetharaman Sridhar
发明人： Seetharaman Sridhar
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/66636 , H01L29/7848
摘要： The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a PMOS device region and NMOS device region. Thereafter, a first gate structure and a second gate structure are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions and activated second source/drain regions, respectively. Additionally, recessed epitaxial carbon doped silicon regions may be formed in the substrate on opposing sides of the second gate structure after annealing.
摘要翻译： 因此，本公开提供了一种半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括提供具有PMOS器件区和NMOS器件区的衬底。 此后，分别在PMOS器件区域和NMOS器件区域上形成第一栅极结构和第二栅极结构。 此外，可以在第一栅极结构的相对侧上的衬底中形成凹入的外延SiGe区域。 此外，第一源极/漏极区域可以形成在第二栅极结构的相对侧上，以及在第二栅极结构的相对侧上的第二源极/漏极区域。 然后可以将第一源极/漏极区域和第二源极/漏极区域退火以分别形成激活的第一源极/漏极区域和激活的第二源极/漏极区域。 此外，在退火之后，可以在第二栅极结构的相对侧上的衬底中形成凹入的外延碳掺杂硅区。
-
5.发明授权公开(公告)号：US07314800B2
公开(公告)日：2008-01-01
申请号：US11296164
申请日：2005-12-07
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
-
6.发明授权Method to selectively recess ETCH regions on a wafer surface using capoly as a mask 有权使用capoly作为掩模来选择性地在晶片表面上凹入ETCH区域的方法公开(公告)号：US07169659B2
公开(公告)日：2007-01-30
申请号：US10931195
申请日：2004-08-31
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7843 , H01L29/7848
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).
摘要翻译： 本发明通过提供制造方法来促进半导体制造，该方法选择性地将应变应用于器件的沟道区，同时减轻所采用的掩模操作。 在半导体器件（102）的NMOS区域上形成CAPOLY层。 在半导体器件（104）的PMOS区域内的器件的有源区域上执行凹蚀刻，并且CAPOLY层防止在半导体器件的NMOS区域内的器件的蚀刻。 随后，执行形成或沉积外延区域并在PMOS区域中的沟道区域上引入第一类型的应变的外延形成工艺（106）。 然后，半导体器件被退火（108）以使CAPOLY层在NMOS区域中的沟道区域上引入第二类型的应变。 退火后，去除CAPOLY层（110）。
-
公开(公告)号：US20050145949A1
公开(公告)日：2005-07-07
申请号：US11054083
申请日：2005-02-08
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L27/02 , H01L27/105 , H01L21/8242 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
-
公开(公告)号：US20120100679A1
公开(公告)日：2012-04-26
申请号：US13274698
申请日：2011-10-17
IPC分类号： H01L21/8238
CPC分类号： H01L21/823456 , H01L21/823462
摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.
摘要翻译： 一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物 或LDMOS晶体管。 一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物， 另一个栅介质层，并保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。
-
公开(公告)号：US20100314670A1
公开(公告)日：2010-12-16
申请号：US12789040
申请日：2010-05-27
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/7846
摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.
摘要翻译： 在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。
-
10.发明授权公开(公告)号：US07662688B2
公开(公告)日：2010-02-16
申请号：US11848187
申请日：2007-08-30
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.017 秒)
