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1.发明申请公开(公告)号：US20080003772A1
公开(公告)日：2008-01-03
申请号：US11848187
申请日：2007-08-30
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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2.发明授权公开(公告)号：US08067279B2
公开(公告)日：2011-11-29
申请号：US12489223
申请日：2009-06-22
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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3.发明申请公开(公告)号：US20090258471A1
公开(公告)日：2009-10-15
申请号：US12489223
申请日：2009-06-22
IPC分类号： H01L21/8244 , H01L21/762
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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4.发明授权公开(公告)号：US07193277B2
公开(公告)日：2007-03-20
申请号：US11054083
申请日：2005-02-08
IPC分类号： H01L21/44
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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公开(公告)号：US20060084230A1
公开(公告)日：2006-04-20
申请号：US11296164
申请日：2005-12-07
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
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6.发明授权公开(公告)号：US07314800B2
公开(公告)日：2008-01-01
申请号：US11296164
申请日：2005-12-07
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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公开(公告)号：US20050145949A1
公开(公告)日：2005-07-07
申请号：US11054083
申请日：2005-02-08
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L27/02 , H01L27/105 , H01L21/8242 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
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8.发明授权公开(公告)号：US07662688B2
公开(公告)日：2010-02-16
申请号：US11848187
申请日：2007-08-30
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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9.发明授权公开(公告)号：US07141468B2
公开(公告)日：2006-11-28
申请号：US10694237
申请日：2003-10-27
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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10.发明申请公开(公告)号：US20050087810A1
公开(公告)日：2005-04-28
申请号：US10694237
申请日：2003-10-27
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L27/02 , H01L27/105 , H01L21/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。
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