发明申请
- 专利标题： Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die
- 专利标题（中）： 集成电路芯片和集成电路芯片的测试方法
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申请号： US12113881申请日： 2008-05-01
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公开(公告)号： US20090273007A1公开(公告)日： 2009-11-05
- 发明人: Kangping Zhang , Fong-Long Lin
- 申请人： Kangping Zhang , Fong-Long Lin
- 专利权人： Silicon Storage Tech., Inc.
- 当前专利权人： Silicon Storage Tech., Inc.
- 主分类号： H01L27/10
- IPC分类号： H01L27/10 ; H01L21/66
摘要：
In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
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