公开(公告)号：US20100226170A1

公开(公告)日：2010-09-09

申请号：US12398913

申请日：2009-03-05

申请人： Fong-Long Lin ,  Tingniu Deng

发明人： Fong-Long Lin ,  Tingniu Deng

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C5/14

CPC分类号： G11C5/141 ,  G11C5/143 ,  G11C5/144 ,  G11C16/22

摘要： An electrically programmable non-volatile memory device comprises a memory circuit which includes an array of non-volatile memory cells. Each memory cell is capable of being programmed. A programming circuit can generate a programming signal to program one or more of the memory cells. A voltage detector circuit is connected to a voltage source which outputs a certain voltage. The voltage detector circuit detects when the certain voltage has decreased to a certain level, and in response thereto, the voltage detector provides an output signal to the memory controller to complete the on-going programming command sequence and to power down itself. An auxiliary voltage source maintains voltage to the memory circuit for a period of time sufficient for the programming circuit to complete the programming of the one or more of the memory cells, when the certain voltage is at or below the certain level.

摘要翻译： 一种电可编程的非易失性存储器件包括一个包括非易失性存储器单元阵列的存储器电路。 每个存储单元都能被编程。 编程电路可以产生编程信号以编程一个或多个存储器单元。 电压检测器电路连接到输出一定电压的电压源。 电压检测器电路检测某一电压何时降低到一定水平，并且响应于此，电压检测器向存储器控制器提供输出信号以完成正在进行的编程命令序列并使其自身断电。 当一定电压处于或低于某一水平时，辅助电压源将电压维持到存储器电路一段足以使编程电路完成一个或多个存储器单元的编程的时间。

公开(公告)号：US07724568B2

公开(公告)日：2010-05-25

申请号：US12040707

申请日：2008-02-29

申请人： Siamak Arya ,  Fong-Long Lin

发明人： Siamak Arya ,  Fong-Long Lin

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

摘要翻译： 存储器件包括易受读取干扰的非易失性电可变存储器。 该装置具有用于控制非易失性存储器的操作的控制电路。 该设备还具有第一易失性缓存存储器。 第一易失性高速缓冲存储器连接到控制电路，并且用于存储要写入或从非易失性存储器读取的数据作为存储器件的高速缓存。 该设备还具有第二易失性缓存存储器。 第二易失性高速缓存存储器连接到控制电路，用于存储从非易失性存储器读取的数据作为存储器件的读高速缓存。 最后，在来自第一易失性高速缓存存储器的数据未命中的情况下，控制电路从第二易失性高速缓冲存储器读取数据，并且在从第一和第二易失性高速缓存存储器发生数据丢失的情况下从非易失性存储器读取数据 。

公开(公告)号：US20100125444A1

公开(公告)日：2010-05-20

申请号：US12272710

申请日：2008-11-17

申请人： Siamak Arya ,  Fong-Long Lin

发明人： Siamak Arya ,  Fong-Long Lin

IPC分类号： G06F9/455 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： A NOR emulating memory device has a memory controller with a first bus for receiving a NOR command signal, and for servicing a read operation from a desired address in a NOR memory. The memory controller has a second bus for communicating with a NAND memory in a NAND memory protocol, and a third bus for communicating with a RAM memory. A NAND memory is connected to the second bus. The NAND memory has an array of memory cells divided into a plurality of pages with each page divided into a plurality of sectors, with each sector having a plurality of bits. The NAND memory further has a page buffer for storing a page of bits read from the array during the read operation of the NAND memory. A RAM memory is connected to the third bus. The memory controller has a NOR memory for storing program code for initiating the operation of the memory controller, and for receiving NOR commands from the first bus and issuing NAND protocol commands on the second bus, in response thereto, to emulate the operation of a NOR memory device. The program code causes the memory controller to read a first sector of bits from the page buffer of the NAND memory and to write the sector of bits into the RAM memory, wherein the first sector contains the location of the desired address, and supplying data from said RAM memory in response to the read operation.

摘要翻译： NOR仿真存储器件具有存储器控制器，其具有用于接收NOR命令信号的第一总线，并用于从NOR存储器中的期望地址服务于读取操作。 存储器控制器具有用于与NAND存储器协议中的NAND存储器通信的第二总线，以及用于与RAM存储器通信的第三总线。 NAND存储器连接到第二总线。 NAND存储器具有分成多个页面的存储器单元的阵列，每个页被分成多个扇区，每个扇区具有多个位。 NAND存储器还具有用于在NAND存储器的读取操作期间存储从阵列读取的位的页面的页面缓冲器。 RAM存储器连接到第三总线。 存储器控制器具有NOR存储器，用于存储用于启动存储器控制器的操作的程序代码，并且用于从第一总线接收NOR命令并在第二总线上发出NAND协议命令，以响应于此来仿真NOR的操作 存储设备。 程序代码使得存储器控制器从NAND存储器的页面缓冲器中读取第一个比特位，并将比特扇区写入RAM存储器，其中第一个扇区包含所需地址的位置，并从 所述RAM存储器响应于读操作。

公开(公告)号：US20100199020A1

公开(公告)日：2010-08-05

申请号：US12365829

申请日：2009-02-04

申请人： Fong-Long Lin ,  Prasanth Kumar ,  Dongsheng Xing

发明人： Fong-Long Lin ,  Prasanth Kumar ,  Dongsheng Xing

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： In the present invention a non-volatile memory subsystem comprises a non-volatile memory device and a memory controller. The memory controller controls the operation of the non-volatile memory device with the memory controller having a processor for executing computer program instructions for partitioning the non-volatile memory device into a plurality of partitions, with each partition having adjustable parameters for wear level and data retention. The memory subsystem also comprises a clock for supplying timing signals to the memory controller.

摘要翻译： 在本发明中，非易失性存储器子系统包括非易失性存储器件和存储器控制器。 存储器控制器控制非易失性存储器设备的操作，存储器控制器具有用于执行用于将非易失性存储器设备划分成多个分区的计算机程序指令的处理器，每个分区具有用于磨损水平和数据的可调参数 保留。 存储器子系统还包括用于向存储器控制器提供定时信号的时钟。

公开(公告)号：US20100138588A1

公开(公告)日：2010-06-03

申请号：US12326811

申请日：2008-12-02

申请人： Fong Long Lin ,  Je-Hurn Shieh

发明人： Fong Long Lin ,  Je-Hurn Shieh

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G11C16/3418

摘要： A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.

摘要翻译： 控制器操作具有非易失性存储器单元阵列的NAND非易失性存储器件。 非易失性存储器单元的阵列容易受到存储在阵列的一个或多个存储器单元中的数据的损失。 控制器与主机设备接口，并从主机设备接收时间戳信号。 控制器包括处理器和存储有程序代码的存储器，用于由处理器执行。 程序代码被配置为由控制器接收来自主机设备的时间戳信号; 将所接收的时间戳信号与存储的信号进行比较，其中所存储的信号是控制器从主机设备及时接收到的时间戳信号; 并且基于比较步骤确定何时对存储在存储器阵列中的数据执行数据保留和刷新操作。

公开(公告)号：US20100125696A1

公开(公告)日：2010-05-20

申请号：US12272693

申请日：2008-11-17

申请人： Prasanth Kumar ,  Dongsheng Xing ,  Fong-Long Lin

发明人： Prasanth Kumar ,  Dongsheng Xing ,  Fong-Long Lin

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7211

摘要： A memory controller controls the operation of a non-volatile memory device. The memory device has a data storage section and an erased storage section. The data storage section has a first plurality of blocks and the erased storage section has a second plurality of blocks. Each of the first and second plurality of blocks has a plurality of non-volatile memory bits that are erased together. Further, each block has an associated counter for storing the number of times the block has been erased. The memory controller has program instructions which are to scan the counters associated with the blocks of the first plurality of blocks based upon the count contained in each of the counters associated therewith to select a third block, and to scan the counters associated with the blocks of the second plurality of blocks based upon the count contained in each of the counters associated therewith to select a fourth block. The program instructions are further configured to transfer data from the third block to the fourth block, and associating said fourth block with said first plurality of blocks. Finally the program instructions are configured to erase said third block and incrementing the counter associated with said third block, and associating said third block with said second plurality of blocks. The present invention is also a method of operating a non-volatile memory device in accordance with the above described steps.

摘要翻译： 存储器控制器控制非易失性存储器件的操作。 存储装置具有数据存储部和擦除存储部。 数据存储部具有第一多个块，并且擦除存储部具有第二多个块。 第一和第二多个块中的每一个具有一起被擦除的多个非易失性存储器位。 此外，每个块具有用于存储块被擦除次数的关联计数器。 存储器控制器具有程序指令，其基于与其相关联的每个计数器中包含的计数来扫描与第一多个块的块相关联的计数器，以选择第三块，并且扫描与块相关联的计数器 基于与其相关联的每个计数器中包含的计数来选择第四块，所述第二多个块。 程序指令还被配置为将数据从第三块传送到第四块，并将所述第四块与所述第一多个块相关联。 最后，程序指令被配置为擦除所述第三块并递增与所述第三块相关联的计数器，并且将所述第三块与所述第二多个块相关联。 本发明也是根据上述步骤操作非易失性存储器件的方法。

公开(公告)号：US20090273007A1

公开(公告)日：2009-11-05

申请号：US12113881

申请日：2008-05-01

申请人： Kangping Zhang ,  Fong-Long Lin

发明人： Kangping Zhang ,  Fong-Long Lin

IPC分类号： H01L27/10 ,  H01L21/66

CPC分类号： G01R31/2884

摘要： In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

摘要翻译： 在本发明中，公开了一种无包装集成电路管芯的测试方法。 管芯具有多个第一输入/输出焊盘。 在管芯中的不是第一多个（以下称为“第二多个”）的所有管芯的输入/输出焊盘之间在管芯中制造串联电连接。 第二组具有开始输入和结束输出。 第二多个的开始输入连接到第一多个输入焊盘的一个选择的输入缓冲器的输出，并且第二多个的输出端的输出也连接到第一多个的一个选择的输出焊盘的输入。 通过所选择的输入焊盘和第一组的选定的输出焊盘来测试第二组输入/输出焊盘，而不需要在晶片分类期间接触电探针。 本发明还涉及一种如此制造的便于测试的集成电路管芯。

公开(公告)号：US20070233933A1

公开(公告)日：2007-10-04

申请号：US11637419

申请日：2006-12-11

申请人： Jeremy Wang ,  Fong-Long Lin ,  Bing Yeh

发明人： Jeremy Wang ,  Fong-Long Lin ,  Bing Yeh

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0638 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/225 ,  Y02D10/13

摘要： A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

摘要翻译： 使用控制器和NAND存储器的NOR仿真装置可以在主存储器中放置的计算机系统中使用或代替BIOS NOR存储器。 因此，仿真装置可以用作可引导存储器。 此外，该设备可以充当硬盘驱动器的缓存。 此外，通过在设备中添加MP3播放器控制器，即使在PC关闭或处于休眠模式时，该设备也可以作为独立的音频播放设备。 最后使用MP3播放器控制器，设备可以访问存储在硬盘驱动器上的附加音频数据，同时PC处于关闭模式或休眠模式。 最后，即使在PC关闭或处于休眠模式，并且控制连接到其上的USB端口，该设备也可以用于操作磁盘驱动器。

公开(公告)号：US20070147115A1

公开(公告)日：2007-06-28

申请号：US11637420

申请日：2006-12-11

申请人： Fong-Long Lin ,  Bing Yeh

发明人： Fong-Long Lin ,  Bing Yeh

IPC分类号： G11C14/00

CPC分类号： G06F13/1694

摘要： A memory device has a controller. The controller has a first address bus for receiving a RAM address signals, a first data bus for receiving RAM data signals, and a first control bus for receiving RAM control signals. The controller further has a second address bus for interfacing with a volatile RAM memory, a second data bus for interfacing with the volatile RAM memory, and a second control bus for interfacing with the volatile RAM memory. The controller further has a third address/data bus for interfacing with a non-volatile NAND memory, and a third control bus for interfacing with non-volatile NAND memory. The memory device further having a RAM memory connected to said second address bus, said second data bus, and said second control bus. The memory device further having a non-volatile NAND memory connected to the third address/data bus and to the third control bus. The controller also has a non-volatile bootable memory, and further has means to receive a first address on the first address bus and to map the first address to a second address in the non-volatile NAND memory, with the volatile RAM memory serving as cache for data to or from the second address in the non-volatile NAND memory, and means for maintaining data coherence between the data stored in the volatile RAM memory as cache and the data at the second address in the non-volatile NAND memory.

摘要翻译： 存储器件具有控制器。 控制器具有用于接收RAM地址信号的第一地址总线，用于接收RAM数据信号的第一数据总线和用于接收RAM控制信号的第一控制总线。 控制器还具有用于与易失性RAM存储器连接的第二地址总线，用于与易失性RAM存储器接口的第二数据总线，以及用于与易失性RAM存储器对接的第二控制总线。 控制器还具有用于与非易失性NAND存储器连接的第三地址/数据总线，以及用于与非易失性NAND存储器进行接口的第三控制总线。 所述存储装置还具有连接到所述第二地址总线，所述第二数据总线和所述第二控制总线的RAM存储器。 存储器件还具有连接到第三地址/数据总线和第三控制总线的非易失性NAND存储器。 控制器还具有非易失性可引导存储器，并且还具有在第一地址总线上接收第一地址并将第一地址映射到非易失性NAND存储器中的第二地址的装置，其中易失性RAM存储器用作 用于将数据缓存到非易失性NAND存储器中的第二地址的数据，以及用于将存储在易失性RAM存储器中的数据之间的数据相干度保持为高速缓存和非易失性NAND存储器中的第二地址处的数据的装置。

公开(公告)号：US07146442B2

公开(公告)日：2006-12-05

申请号：US11407601

申请日：2006-04-19

申请人： Eugene Feng ,  William Lau ,  Fong-Long Lin

发明人： Eugene Feng ,  William Lau ,  Fong-Long Lin

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G06F13/4243

摘要： A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

摘要翻译： 计算机系统的主板具有视频显示端口，可再编程非易失性存储器，用于非易失性存储器的控制器，以及用于向视频显示端口输出视频信号的图形控制器电路。 有线电路将图形控制器电路连接到控制器到端口。 因此，可以使用视频显示端口将来自计算机系统的视频信号输出到外围视频显示装置，并且视频显示端口可以用作输入端口以重新编程非易失性存储器。 本发明还涉及一种具有非易失性存储器单元阵列和用于与其通信的两个端口的非易失性存储器件。 第一端口接收第一通信协议并与第一通信协议中的阵列接口。 第二端口接收第二通信协议并将第二通信协议转换为第一通信协议。