发明申请
- 专利标题: Wirebondless Wafer Level Package with Plated Bumps and Interconnects
- 专利标题(中): 无铅晶圆级封装,镀层冲击和互连
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申请号: US12126548申请日: 2008-05-23
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公开(公告)号: US20090289356A1公开(公告)日: 2009-11-26
- 发明人: Zigmund R. Camacho , Dioscoro A. Merilo , Lionel Chien Hui Tay , Jose A. Caparas
- 申请人: Zigmund R. Camacho , Dioscoro A. Merilo , Lionel Chien Hui Tay , Jose A. Caparas
- 申请人地址: SG Singapore
- 专利权人: STATS ChipPAC, Ltd.
- 当前专利权人: STATS ChipPAC, Ltd.
- 当前专利权人地址: SG Singapore
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L21/02
摘要:
A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. Underfill material is deposited into the die cavity between the semiconductor die and a surface of the die cavity. In one embodiment, a passivation layer is deposited over the semiconductor die, and a portion of the passivation layer is etched to expose a contact pad of the semiconductor die. A metal layer is deposited over the package. The metal layer forms a package bump and a plated interconnect between the package bump and the contact pad of the semiconductor die. Encapsulant is deposited over the semiconductor package.
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