发明申请
US20090289356A1 Wirebondless Wafer Level Package with Plated Bumps and Interconnects 有权
无铅晶圆级封装,镀层冲击和互连

Wirebondless Wafer Level Package with Plated Bumps and Interconnects
摘要:
A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. Underfill material is deposited into the die cavity between the semiconductor die and a surface of the die cavity. In one embodiment, a passivation layer is deposited over the semiconductor die, and a portion of the passivation layer is etched to expose a contact pad of the semiconductor die. A metal layer is deposited over the package. The metal layer forms a package bump and a plated interconnect between the package bump and the contact pad of the semiconductor die. Encapsulant is deposited over the semiconductor package.
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