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发明申请
US20090294983A1 HYBRID CONDUCTIVE VIAS INCLUDING SMALL DIMENSION ACTIVE SURFACE ENDS AND LARGER DIMENSION BACK SIDE ENDS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND ASSOCIATED METHODS 有权
混合导电六角包括小尺寸有源表面端和大尺寸背面，包括其的半导体器件及相关方法

  • 专利标题： HYBRID CONDUCTIVE VIAS INCLUDING SMALL DIMENSION ACTIVE SURFACE ENDS AND LARGER DIMENSION BACK SIDE ENDS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND ASSOCIATED METHODS
  • 专利标题（中）： 混合导电六角包括小尺寸有源表面端和大尺寸背面，包括其的半导体器件及相关方法
  • 申请号： US12052418
    申请日： 2008-06-03
  • 公开(公告)号： US20090294983A1
    公开(公告)日： 2009-12-03
  • 发明人: Chad A. Cobbley , Jonathon G. Greenwood
  • 申请人： Chad A. Cobbley , Jonathon G. Greenwood
  • 申请人地址： US ID Boise
  • 专利权人： MICRON TECHNOLOGY, INC.
  • 当前专利权人： MICRON TECHNOLOGY, INC.
  • 当前专利权人地址： US ID Boise
  • 主分类号： H01L23/48
  • IPC分类号： H01L23/48 ;  H01L21/4763
HYBRID CONDUCTIVE VIAS INCLUDING SMALL DIMENSION ACTIVE SURFACE ENDS AND LARGER DIMENSION BACK SIDE ENDS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND ASSOCIATED METHODS
摘要：
A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed.
摘要（中）：

半导体器件的导电通孔包括延伸到制造衬底的有源表面的相对小的直径部分和延伸到制造衬底的背侧的对应的相对较大的直径部分。 这种类型的导电通孔可以通过在BEOL处理之前或期间形成相对较小的直径部分来制造，而每个导电通孔的大直径部分可以在BEOL处理完成之后制造。 还公开了包括具有这种导电通孔的一个或多个半导体器件的电子器件。

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