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    Method and apparatus for solder sphere placement using an air knife
    2.
    发明授权
    Method and apparatus for solder sphere placement using an air knife 失效
    使用气刀进行焊球放置的方法和装置

    公开(公告)号：US5431332A

    公开(公告)日：1995-07-11

    申请号：US192880

    申请日：1994-02-07

    申请人： Thomas P. Kirby ,  Jonathon G. Greenwood ,  Edward Juchniewicz ,  Ovidiu Neiconi

    发明人： Thomas P. Kirby ,  Jonathon G. Greenwood ,  Edward Juchniewicz ,  Ovidiu Neiconi

    IPC分类号： B23K1/20 ,  B23K35/14 ,  H01L21/48 ,  H05K3/34 ,  B23K1/00 ,  B23K3/08

    CPC分类号： B23K1/20 ,  H01L21/4853 ,  H05K3/3478 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/742 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/0557 ,  H05K2203/081

    摘要： A station (10) in a manufacturing line (12) for the accurate placement of solder balls (30) on a ball grid array package and for the removal of excess solder balls comprises a substrate (4) having an array of solder pads (7), and an adhesion layer (8) on the solder pads. The station further comprises a stencil (16) placed on top of the substrate and having a height between 1/4 times the diameter of one of the solder balls and 5/4 times the diameter of one of the balls, the stencil having an array of apertures (18) corresponding to the array of solder pads and substantially exposing each of the solder pads of the array, a pallet (2) for holding and transporting the substrate to the stencil and further along the manufacturing line, a dispenser (26) for pouring solder balls in bulk over the stencil, a vibration device (20) coupled to the station for urging the solder balls into the apertures of the stencil and onto the adhesion layer above the solder pads, and a moving directed column of air (24) across the surface of the stencil to remove excess solder balls from the stencil.

    摘要翻译： 用于将焊球（30）精确放置在球栅阵列封装上并用于去除多余焊球的生产线（12）中的工位（10）包括具有焊盘阵列（7）的衬底（4） ）和焊盘上的粘附层（8）。 该站还包括设置在基板顶部上的模板（16），其高度为焊料球之一的直径的1/4倍和其中一个球的直径的5/4倍，该模板具有阵列 的对应于焊盘阵列的孔（18），并且基本上暴露阵列的每个焊盘;托架（2），用于将衬底保持并传送到模板，并且还沿着生产线，分配器（26） 用于将焊球大量地浇注在模板上;振动装置（20），其联接到所述工位，用于将焊球推动到模板的孔中并且到达焊盘上方的粘合层，以及移动的定向柱空气（24 ）穿过模板的表面以从模板去除多余的焊球。

    LIGHT EMITTING DIODE WAFER-LEVEL PACKAGE WITH SELF-ALIGNING FEATURES
    4.
    发明申请
    LIGHT EMITTING DIODE WAFER-LEVEL PACKAGE WITH SELF-ALIGNING FEATURES 有权
    具有自亮特性的发光二极管水平封装

    公开(公告)号：US20110220925A1

    公开(公告)日：2011-09-15

    申请号：US12721016

    申请日：2010-03-10

    申请人： Jonathon G. Greenwood

    发明人： Jonathon G. Greenwood

    IPC分类号： H01L33/00

    CPC分类号： H01L33/48 ,  H01L24/97 ,  H01L33/0079 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. A patterned wafer has a plurality of individual LED attachment sites, and an alignment wafer has a plurality of individual cavities. The patterned wafer and the alignment wafer are superimposed with the LED attachment sites corresponding generally to the cavities of the alignment wafer. At least one LED is placed in the cavities using the cavity to align the LED relative to the patterned wafer. The LED is electrically connected to contacts on the patterned wafer, and a phosphor layer is formed in the cavity to cover at least a part of the LED.

    摘要翻译： 本文公开了包括具有空腔的基板的发光二极管封装结构的几个实施例。 图案化晶片具有多个单独的LED附接位置，并且对准晶片具有多个单独的空腔。 图案化晶片和对准晶片与通常对准晶片的腔的LED附着位置叠加。 使用空腔将至少一个LED放置在空腔中，以使LED相对于图案化晶片对准。 LED电连接到图案化晶片上的触点，并且在空腔中形成荧光体层以覆盖LED的至少一部分。

    Making chip size semiconductor packages
    6.
    发明授权
    Making chip size semiconductor packages 有权
    制造芯片尺寸的半导体封装

    公开(公告)号：US06338985B1

    公开(公告)日：2002-01-15

    申请号：US09498144

    申请日：2000-02-04

    申请人： Jonathon G. Greenwood

    发明人： Jonathon G. Greenwood

    IPC分类号： H01L2144

    CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/97 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A method for making low cost chip size semiconductor packages (“CSPs”) includes preparing a substrate having a first surface with metal pads and lands thereon, and an opposite second surface having openings in it through which the lands are exposed. A solder mask is formed over the first surface of the substrate, and has apertures in it through which the metal pads are exposed. At least one vent opening is formed through the substrate and solder mask. A semiconductor die is electrically connected to the substrate through the apertures in the solder mask using the “flip chip” connection method. A body of an insulative plastic material is formed on the surface of the solder mask that simultaneously overmolds the die and underfills the space between the solder mask and the die in a single step. Solder balls are attached to the lands through the openings in the second surface of the substrate to serve as package input/output terminals.

    摘要翻译： 用于制造低成本芯片尺寸半导体封装（“CSP”）的方法包括制备具有第一表面的衬底，其上具有金属焊盘和焊盘，以及具有开口的相对的第二表面，焊盘暴露在该第二表面上。 在衬底的第一表面上形成焊接掩模，并且在其中具有孔，金属焊盘通过该孔露出。 至少有一个通气孔通过衬底和焊接掩模形成。 使用“倒装芯片”连接方法，半导体管芯通过焊料掩模中的孔电连接到基板。 在焊接面的表面上形成绝缘塑料材料体，同时包覆模具，并在一个步骤中对焊接掩模和模具之间的空间进行底部填充。 焊球通过衬底的第二表面中的开口附接到焊盘，用作封装输入/输出端子。

    Method for plating a substrate to eliminate the use of a solder mask
    7.
    发明授权
    Method for plating a substrate to eliminate the use of a solder mask 失效
    电镀基板以消除使用焊接掩模的方法

    公开(公告)号：US5716760A

    公开(公告)日：1998-02-10

    申请号：US810272

    申请日：1997-03-03

    申请人： Frank Juskey ,  Jonathon G. Greenwood ,  Douglas W. Hendricks

    发明人： Frank Juskey ,  Jonathon G. Greenwood ,  Douglas W. Hendricks

    IPC分类号： H05K3/18 ,  H05K3/24 ,  H05K3/34 ,  G03F7/00

    CPC分类号： H05K3/243 ,  H05K3/3452 ,  H05K2201/2081 ,  H05K2203/0315 ,  H05K3/184

    摘要： A novel process for plating a substrate without solder mask wherein the substrate is coated with a polymer catalyst to assist adhesion of conductive metal to the substrate. Next, a first plating mask photopolymer, or plating resist, is coated over the polymer catalyst, a circuit pattern is imaged onto the first plating mask and the first plating mask is developed to reveal windows, or circuit traces, in the first plating mask corresponding to the circuit pattern to be embodied on the substrate. Thereafter, a first conductive material such as copper is plated into the windows, and, thereafter, a second conductive material such as nickel may be plated into the windows on top of the first conductive material. Then, the first plating mask is removed from the substrate, leaving behind the conductive material in the form of the desired circuit pattern. Next, a second plating mask photopolymer is formed over the substrate and conductive materials, and an I/O interconnect mask corresponding to the I/O interconnect pads is photo-optically imaged onto the second plating mask and the second plating mask is developed to remove portions thereof, creating "interconnect voids," corresponding to the interconnect pads. Thereafter, a third conductive material such as gold is plated into the interconnect voids to create conductive I/O pads.

    摘要翻译： 一种用于电镀不具有阻焊掩模的衬底的新方法，其中衬底涂覆有聚合物催化剂以辅助将导电金属粘附到衬底上。 接下来，将第一电镀掩模光聚合物或电镀抗蚀剂涂覆在聚合物催化剂上，将电路图案成像到第一电镀掩模上，并且将第一电镀掩模显影以在第一电镀掩模中显示相应的窗口或电路迹线 涉及要在基板上体现的电路图案。 此后，将诸如铜的第一导电材料电镀到窗口中，此后可以将第二导电材料如镍电镀在第一导电材料顶部的窗口中。 然后，从基板去除第一电镀掩模，以期望的电路图案的形式留下导电材料。 接下来，在基板上形成第二电镀掩模光聚合物和导电材料，并且对应于I / O互连焊盘的I / O互连掩模被光学成像到第二电镀掩模上，并且第二电镀掩模被显影以除去 其部分，产生对应于互连焊盘的“互连空隙”。 此后，将诸如金的第三导电材料电镀到互连空隙中以产生导电I / O焊盘。

    Light emitting diode wafer-level package with self-aligning features
    9.
    发明授权
    Light emitting diode wafer-level package with self-aligning features 有权
    发光二极管晶圆级封装具有自对准功能

    公开(公告)号：US08441020B2

    公开(公告)日：2013-05-14

    申请号：US12721016

    申请日：2010-03-10

    申请人： Jonathon G. Greenwood

    发明人： Jonathon G. Greenwood

    IPC分类号： H01L33/00

    CPC分类号： H01L33/48 ,  H01L24/97 ,  H01L33/0079 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. A patterned wafer has a plurality of individual LED attachment sites, and an alignment wafer has a plurality of individual cavities. The patterned wafer and the alignment wafer are superimposed with the LED attachment sites corresponding generally to the cavities of the alignment wafer. At least one LED is placed in the cavities using the cavity to align the LED relative to the patterned wafer. The LED is electrically connected to contacts on the patterned wafer, and a phosphor layer is formed in the cavity to cover at least a part of the LED.

    摘要翻译： 本文公开了包括具有空腔的基板的发光二极管封装结构的几个实施例。 图案化晶片具有多个单独的LED附接位置，并且对准晶片具有多个单独的空腔。 图案化晶片和对准晶片与通常对准晶片的腔的LED附着位置叠加。 使用空腔将至少一个LED放置在空腔中，以使LED相对于图案化晶片对准。 LED电连接到图案化晶片上的触点，并且在空腔中形成荧光体层以覆盖LED的至少一部分。