Invention Application
US20090305502A1 Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby
有权
形成集成电路芯片的方法,其具有垂直扩展的通过基板的通孔和由此形成的芯片
- Patent Title: Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby
- Patent Title (中): 形成集成电路芯片的方法,其具有垂直扩展的通过基板的通孔和由此形成的芯片
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Application No.: US12476793Application Date: 2009-06-02
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Publication No.: US20090305502A1Publication Date: 2009-12-10
- Inventor: Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
- Applicant: Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
- Priority: KR2008-54124 20080610
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
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