A system for reducing peaks comprises a processor and a memory. The processor is configured to determine a phase offset for each of a plurality of input signals. The phase offset for each of the plurality of input signals are determined using one or more trials of phase offsets to determine a selected set of phase offsets. The processor is further configured to modulate the plurality of input data signals using the selected set of phase offsets to produce a plurality of modulated phase offset data signals and to generate a sum of the plurality of modulated phase offset data signals, wherein the sum has a lower peak value during a trial of the one or more trials of phase offsets as compared to the sum during another trial not using the selected set of phase offset signals. The memory is coupled to the processor and configured to provide the processor with instructions.