发明申请
- 专利标题： METHOD OF FABRICATING A GATE STRUCTURE
- 专利标题（中）： 制作门结构的方法
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申请号： US12544425申请日： 2009-08-20
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公开(公告)号： US20090311855A1公开(公告)日： 2009-12-17
- 发明人: Richard A. Bruff , Richard A. Conti , Denise Pendleton-Lipinski , Amanda L. Tessier , Brian L. Tessier , Yun-Yu Wang , Daewon Yang , Chienfan Yu
- 申请人： Richard A. Bruff , Richard A. Conti , Denise Pendleton-Lipinski , Amanda L. Tessier , Brian L. Tessier , Yun-Yu Wang , Daewon Yang , Chienfan Yu
- 主分类号： H01L21/28
- IPC分类号： H01L21/28
摘要：
A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.
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