A process of an embedded chip package structure includes following steps. Firstly, a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a number of through holes are provided. The opening and the through holes connect the first surface and the second surface. A chip is then disposed in the opening. Next, a dielectric layer is formed in the opening and the through holes to fix the chip in the opening. Thereafter, a number of conductive vias are respectively formed in the through holes and insulated from the metal core layer by a portion of the dielectric layer located in the through holes. A circuit structure is then formed on the first surface of the metal core layer by performing a build-up process, and the circuit structure electrically connects the chip and the conductive vias.