发明申请
US20100006986A1 Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions
有权
半导体器件布局包括具有限制门极电极布局的电池布局，具有矩形形状的栅极电极布局特征定义为具有相应的非对称扩散区域的至少四个栅极电极轨迹
- 专利标题： Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions
- 专利标题（中）： 半导体器件布局包括具有限制门极电极布局的电池布局，具有矩形形状的栅极电极布局特征定义为具有相应的非对称扩散区域的至少四个栅极电极轨迹
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申请号： US12561216申请日： 2009-09-16
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公开(公告)号： US20100006986A1公开(公告)日： 2010-01-14
- 发明人: Scott T. Becker , Michael C. Smayling
- 申请人： Scott T. Becker , Michael C. Smayling
- 申请人地址： US CA Campbell
- 专利权人： Tela Innovations, Inc.
- 当前专利权人： Tela Innovations, Inc.
- 当前专利权人地址： US CA Campbell
- 主分类号： H01L23/528
- IPC分类号： H01L23/528 ; H01L23/52
摘要：
A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout of the restricted layout region. The plurality of diffusion region layout shapes include a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. A gate electrode level layout is defined include a number of rectangular-shaped layout features placed to extend in only a first parallel direction, and defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.
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