公开(公告)号：US10217763B2

公开(公告)日：2019-02-26

申请号：US16119727

申请日：2018-08-31

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Michael C. Smayling

IPC分类号： H01L21/70 ,  H01L29/76 ,  H01L27/118 ,  H01L27/092 ,  H01L21/28 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50

摘要： An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

公开(公告)号：US09905576B2

公开(公告)日：2018-02-27

申请号：US15696728

申请日：2017-09-06

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Michael C. Smayling

IPC分类号： H01L27/118 ,  H01L29/423 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  G06F17/50 ,  H01L21/28 ,  H01L23/528

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/28123 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/42376 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/11862 ,  H01L2027/11864 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

公开(公告)号：US09871056B2

公开(公告)日：2018-01-16

申请号：US15389883

申请日：2016-12-23

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： G11C11/412 ,  H01L27/118 ,  H01L27/11 ,  G11C5/06 ,  H01L27/02 ,  H01L27/092 ,  G06F17/50 ,  H01L27/088 ,  H01L23/538 ,  H01L23/498 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/105

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

公开(公告)号：US09536899B2

公开(公告)日：2017-01-03

申请号：US14945361

申请日：2015-11-18

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： G11C11/412 ,  H01L27/118 ,  H01L27/11 ,  G11C5/06 ,  H01L27/02 ,  H01L27/092 ,  G06F17/50 ,  H01L27/088 ,  H01L23/538 ,  H01L23/498 ,  H01L21/8234 ,  H01L23/528

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

摘要翻译： 第一导电结构形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二导电结构形成第一晶体管类型的第二晶体管的栅电极。 第三导电结构形成第二晶体管类型的第二晶体管的栅电极。 第四导电结构形成第一晶体管类型的第三晶体管的栅电极。 第五导电结构形成第二晶体管类型的第三晶体管的栅电极。 第六导电结构形成第一晶体管类型的第四晶体管的栅电极和第二晶体管类型的第四晶体管。 第一晶体管类型的第二和第三晶体管和第二晶体管类型的第二和第三晶体管电连接以形成交叉耦合晶体管配置。

公开(公告)号：US09425145B2

公开(公告)日：2016-08-23

申请号：US14987723

申请日：2016-01-04

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker

IPC分类号： H01L23/528 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/423

CPC分类号： H01L27/0207 ,  G03F1/36 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0203 ,  H01L27/088 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/0001

摘要： A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.

摘要翻译： 定义矩形的层间连接布局结构以将第一芯片级的第一布局结构与第二芯片级的第二布局结构电连接。 矩形层间连接布局结构由具有比第一布局结构，第二布局结构或第一布局结构和第二布局结构两者的对应尺寸大至少一个尺寸的截面横截面限定。 矩形层间连接布局结构的尺寸可以在一个方向上超过正常的最大尺寸，以换取在另一个方向上减小的尺寸。 矩形层间连接布局结构可以根据虚拟网格的网格点放置，虚拟网格由两组垂直的虚拟线段组成。 此外，第一和/或第二布局结构可以根据虚拟线的两个垂直组中的一个或两个在空间上定向和/或放置。

公开(公告)号：US09208279B2

公开(公告)日：2015-12-08

申请号：US14303587

申请日：2014-06-12

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L27/11 ,  H01L27/02 ,  H01L27/092 ,  H01L23/538 ,  H01L27/118 ,  H01L23/498

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration.

摘要翻译： 第一线性形状导电结构（LCS）形成第一晶体管类型的第一晶体管的栅电极（GE）。 第二LCS形成第二晶体管类型的第一晶体管的GE。 第三LCS形成第一晶体管类型的第四晶体管的GE。 第四LCS形成第二晶体管类型的第四晶体管的GE。 第一晶体管类型的晶体管通过内部区域与第二晶体管类型的晶体管共同分离。 第一，第二，第三和第四LCS中的每一个具有相应的电连接区域。 第一，第二，第三和第四LCS的至少两个电连接区域位于内部区域内。 第一晶体管类型的第一和第四晶体管以及第二晶体管类型的第一和第四晶体管形成交叉耦合晶体管配置的一部分。

公开(公告)号：US09122832B2

公开(公告)日：2015-09-01

申请号：US12512932

申请日：2009-07-30

申请人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

发明人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并且随后从晶片中移除留下期望的永久结构。

公开(公告)号：US09009641B2

公开(公告)日：2015-04-14

申请号：US13740191

申请日：2013-01-12

申请人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

发明人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

IPC分类号： G06F17/50 ,  H01L27/088 ,  H01L27/092 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L27/0886 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/02521 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/7853 ,  Y02P90/265

摘要： A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.

摘要翻译： 第一晶体管具有在第一扩散鳍内的源区和漏区。 第一扩散鳍片从衬底的表面突出。 第一扩散鳍从第一扩散翅片的第一端到第二端在第一方向上纵向延伸。 第二晶体管具有在第二扩散鳍内的源区和漏区。 第二扩散鳍片从衬底的表面突出。 第二扩散翅片在第一方向上从第二扩散鳍片的第一端部延伸到第二端部的纵向延伸。 第二扩散翅片位于第一扩散鳍的旁边并与之隔开。 第二扩散翅片的第一端或第二端都位于第一扩散鳍片的第一端和第二端之间的第一方向上。

公开(公告)号：US08921896B2

公开(公告)日：2014-12-30

申请号：US13827755

申请日：2013-03-14

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Michael C. Smayling

IPC分类号： H01L27/10 ,  H01L27/02 ,  H01L27/092

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/28123 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/42376 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/11862 ,  H01L2027/11864 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first linear-shaped conductive structure (LSCS) forming gate electrodes of both a first p-transistor and a first n-transistor. A second LSCS forming a gate electrode of a second p-transistor and including an extension portion extending away therefrom. A third LSCS forming a gate electrode of a second n-transistor and including an extension portion extending away therefrom. A fourth LSCS forming a gate electrode of a third p-transistor and including an extension portion extending away therefrom. A fifth LSCS forming a gate electrode of a third n-transistor and including an extension portion extending away therefrom. A sixth LSCS forming gate electrodes of both a fourth p-transistor and a fourth n-transistor. Four contact structures respectively contacting the extension portions of the second, third, fourth, and fifth LSCS's, such that at least two of the extension portions extend different distances beyond their contact structure.

摘要翻译： 形成第一p型晶体管和第一n型晶体管的栅电极的第一线性形状导电结构（LSCS）。 形成第二p晶体管的栅电极并且包括从其延伸的延伸部分的第二LSCS。 第三LSCS形成第二n型晶体管的栅电极，并且包括从其延伸的延伸部分。 形成第三p晶体管的栅电极并且包括从其延伸的延伸部分的第四LSCS。 形成第三n型晶体管的栅电极并且包括从其延伸的延伸部分的第五LSCS。 形成第四p型晶体管和第四n型晶体管的栅电极的第六LSCS。 四个接触结构分别接触第二，第三，第四和第五LSCS的延伸部分，使得至少两个延伸部分延伸超过其接触结构的不同距离。

公开(公告)号：US08872283B2

公开(公告)日：2014-10-28

申请号：US13741305

申请日：2013-01-14

申请人： Tela Innovations, Inc.

发明人： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

摘要翻译： 半导体器件包括栅极电平区域内的导电特征，每个导电特征均由具有平行于第一方向排列的中心线的相应起始矩形布局特征制成。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第一NMOS晶体管器件的栅电极沿着第一栅电极轨道延伸。 第二PMOS和第二NMOS晶体管器件的栅电极沿着第二栅极电极延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。