公开(公告)号：US09563733B2

公开(公告)日：2017-02-07

申请号：US12775429

申请日：2010-05-06

Applicant: Scott T. Becker

Inventor： Scott T. Becker

IPC: G06F17/50 ,  H01L29/76 ,  H01L27/092 ,  H01L27/088 ,  H01L27/02 ,  H01L21/302 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/06 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785 ,  Y02P90/265

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract translation: 公开了电池电路和相应的布局，以包括限定为在第一方向上延伸到衬底上以便彼此平行延伸的线性扩散翅片。 每个线性扩散翅片被限定为沿着它们在第一方向上的尺寸从衬底向上突出。 多个门级结构被限定为在一定数量的线形扩散翅片上以共形方式延伸。 在任何线形扩散翅片上延伸的每个门层结构的部分在基本上垂直于第一方向的第二方向上延伸。 在任何线形扩散翅片上延伸的每个栅极级结构的部分形成相应晶体管的栅电极。 扩散翅片和栅极层结构可以分别根据扩散鳍虚拟栅格和栅极级虚拟栅格放置。

公开(公告)号：US08785979B2

公开(公告)日：2014-07-22

申请号：US12753776

申请日：2010-04-02

Applicant: Scott T. Becker ,  Jim Mali ,  Carole Lambert

Inventor： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC: H01L27/10

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.

Abstract translation: 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 门电极电平区域内的多个导电特征中的每一个由相应的起始矩形布局特征制成，每个起始矩形布局特征的中心线以平行方式排列。 导电特征分别形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一和第二p型扩散区的宽度不同，使得第一和第二PMOS晶体管器件具有不同的宽度。 第一和第二n型扩散区的宽度是不同的，使得第一和第二NMOS晶体管器件具有不同的宽度。 第一和第二PMOS和第一和第二NMOS晶体管器件形成交叉耦合晶体管配置。

公开(公告)号：US08785978B2

公开(公告)日：2014-07-22

申请号：US12753753

申请日：2010-04-02

Applicant: Scott T. Becker ,  Jim Mali ,  Carole Lambert

Inventor： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC: H01L27/10 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.

Abstract translation: 半导体器件包括由在第一和第二p型扩散区域上限定的第一和第二PMOS晶体管以及由第一和第二n型扩散区域限定的第一和第二NMOS晶体管形成的交叉耦合晶体管配置，每个扩散区域 电连接到公共节点。 PMOS和NMOS晶体管的栅极由仅沿第一平行方向延伸的导电特征形成。 第一和第二p型扩散区域中的每一个的至少一部分形成在垂直于第一平行方向延伸的第一公共线上。 第一和第二n型扩散区域相对于第一平行方向以间隔开的方式形成，使得垂直于第一平行方向延伸穿过衬底延伸的单个线的范围与第一和第二n型扩散区域相交 扩散区域。

公开(公告)号：US08742462B2

公开(公告)日：2014-06-03

申请号：US12754103

申请日：2010-04-05

Applicant: Scott T. Becker ,  Jim Mali ,  Carole Lambert

Inventor： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC: H01L27/10 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

Abstract: First and second PMOS transistors are defined over first and second p-type diffusion regions. First and second NMOS transistors are defined over first and second n-type diffusion regions. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.

Abstract translation: 第一和第二PMOS晶体管被限定在第一和第二p型扩散区上。 第一和第二NMOS晶体管被限定在第一和第二n型扩散区上。 每个扩散区电连接到公共节点。 栅极电极由导电特征形成，每个导电特征各自限定在与多个平行栅极电极轨道中的一个唯一相关联并限定的任何一个栅极电平通道内。 第一和第二p型扩散区域中的每一个的至少一部分形成在垂直于第一平行方向延伸的第一公共线上。 第一和第二n型扩散区域相对于第一平行方向以间隔开的方式形成，使得不垂直于第一平行方向延伸穿过衬底延伸的单一线的范围与第一和第二n型扩散区域相交 扩散区域。

公开(公告)号：US08669594B2

公开(公告)日：2014-03-11

申请号：US12753740

申请日：2010-04-02

Applicant: Scott T. Becker ,  Jim Mali ,  Carole Lambert

Inventor： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC: H01L27/10

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

Abstract: First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes of cross-coupled transistors are defined to extend over the diffusion regions in only a first parallel direction, with each gate electrode fabricated from a respective originating rectangular-shaped layout feature. The first and second p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. At least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a common line of extent that extends across the substrate perpendicular to the first parallel direction.

Abstract translation: 第一和第二p型扩散区，以及在半导体器件中形成第一和第二n型扩散区。 每个扩散区电连接到公共节点。 交叉耦合晶体管的栅电极被限定为仅在第一平行方向上在扩散区域上延伸，每个栅电极由相应的起始矩形布局特征制成。 第一和第二p型扩散区域相对于第一平行方向以间隔开的方式形成，使得垂直于第一平行方向延伸穿过衬底延伸的单一线的范围与第一和第二p型扩散区域相交 扩散区域。 第一n型扩散区域的至少一部分和第二n型扩散区域的至少一部分形成在垂直于第一平行方向延伸穿过衬底的共同的范围上。

公开(公告)号：US08667443B2

公开(公告)日：2014-03-04

申请号：US12041584

申请日：2008-03-03

Applicant: Michael C. Smayling ,  Scott T. Becker

Inventor： Michael C. Smayling ,  Scott T. Becker

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/12 ,  H01L27/11807

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract translation: 公开了一种用于定义集成电路设计中使用的多重图案化电池布局的方法。 根据动态阵列架构为单元格的级别定义布局，以便包括多个布局特征。 布局特征的数量是线性的并且通常定向。 布局被拆分为单元格级别的多个子布局。 布局中的布局特征中的每一个都被分配给任何一个子布局。 此外，布局被拆分，使得每个子布局是独立可编制的。 单元级别的子布局存储在计算机可读介质上。

公开(公告)号：US08653857B2

公开(公告)日：2014-02-18

申请号：US12435672

申请日：2009-05-05

Applicant: Scott T. Becker

Inventor： Scott T. Becker

IPC: H03K19/094

CPC classification number: H03K19/20 ,  G06F17/5068 ,  H03K19/215

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract translation: 异或电路包括由第二输入节点控制的传递门。 当通过门被控制时，传递门被连接以将存在于第一输入节点处的逻辑状态的版本传递到输出节点。 传输门由第一输入节点控制。 当这样的控制时，传输门被连接以将存在于第二输入节点的逻辑状态的版本传递到输出节点。 上拉逻辑由第一和第二输入节点控制。 连接上拉逻辑以在第一和第二输入节点都为高电平时驱动输出节点为低电平。 异或电路被定义为类似于异或电路，除了上拉逻辑由下拉逻辑代替，下拉逻辑被连接以在第一和第二输入节点都为高时驱动输出节点为高电平。

公开(公告)号：US08552509B2

公开(公告)日：2013-10-08

申请号：US12754384

申请日：2010-04-05

Applicant: Scott T. Becker ,  Jim Mali ,  Carole Lambert

Inventor： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC: H01L27/092

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract translation: 半导体器件包括导电特征，每个导电特征各自被限定在与多个平行栅极电极轨道中的一个栅极电平通道唯一相关联并且沿着多个平行栅极电极轨迹中 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第一NMOS晶体管器件的栅电极沿着第一栅电极轨道延伸。 第二PMOS和第二NMOS晶体管器件的栅电极分别沿着第二和第三栅电极迹线延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。

公开(公告)号：US08549455B2

公开(公告)日：2013-10-01

申请号：US13540529

申请日：2012-07-02

Applicant: Jonathan R. Quandt ,  Scott T. Becker ,  Dhrumil Gandhi

Inventor： Jonathan R. Quandt ,  Scott T. Becker ,  Dhrumil Gandhi

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

公开(公告)号：US20130249013A1

公开(公告)日：2013-09-26

申请号：US13827755

申请日：2013-03-14

Applicant: Scott T. Becker ,  Michael C. Smayling

Inventor： Scott T. Becker ,  Michael C. Smayling

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/28123 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/42376 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/11862 ,  H01L2027/11864 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first linear-shaped conductive structure (LSCS) forming gate electrodes of both a first p-transistor and a first n-transistor. A second LSCS forming a gate electrode of a second p-transistor and including an extension portion extending away therefrom. A third LSCS forming a gate electrode of a second n-transistor and including an extension portion extending away therefrom. A fourth LSCS forming a gate electrode of a third p-transistor and including an extension portion extending away therefrom. A fifth LSCS forming a gate electrode of a third n-transistor and including an extension portion extending away therefrom. A sixth LSCS forming gate electrodes of both a fourth p-transistor and a fourth n-transistor. Four contact structures respectively contacting the extension portions of the second, third, fourth, and fifth LSCS's, such that at least two of the extension portions extend different distances beyond their contact structure.

Abstract translation: 形成第一p型晶体管和第一n型晶体管的栅电极的第一线性形状导电结构（LSCS）。 形成第二p晶体管的栅电极并且包括从其延伸的延伸部分的第二LSCS。 第三LSCS形成第二n型晶体管的栅电极，并且包括从其延伸的延伸部分。 形成第三p晶体管的栅电极并且包括从其延伸的延伸部分的第四LSCS。 形成第三n型晶体管的栅电极并且包括从其延伸的延伸部分的第五LSCS。 形成第四p型晶体管和第四n型晶体管的栅电极的第六LSCS。 四个接触结构分别接触第二，第三，第四和第五LSCS的延伸部分，使得至少两个延伸部分延伸超过其接触结构的不同距离。