发明申请
US20100019812A1 PLL CIRCUIT, RADIO TERMINAL DEVICE AND CONTROL METHOD OF PLL CIRCUIT 有权
PLL电路,无线电终端设备和PLL电路的控制方法

  • 专利标题: PLL CIRCUIT, RADIO TERMINAL DEVICE AND CONTROL METHOD OF PLL CIRCUIT
  • 专利标题(中): PLL电路,无线电终端设备和PLL电路的控制方法
  • 申请号: US12496065
    申请日: 2009-07-01
  • 公开(公告)号: US20100019812A1
    公开(公告)日: 2010-01-28
  • 发明人: Shinichiro TSUDA
  • 申请人: Shinichiro TSUDA
  • 申请人地址: JP Tokyo
  • 专利权人: Sony Corporation
  • 当前专利权人: Sony Corporation
  • 当前专利权人地址: JP Tokyo
  • 优先权: JP2008-191491 20080724
  • 主分类号: H03L7/06
  • IPC分类号: H03L7/06
PLL CIRCUIT, RADIO TERMINAL DEVICE AND CONTROL METHOD OF PLL CIRCUIT
摘要:
There is provided a PLL circuit including a phase comparison unit that compares an accumulated addition value of a division ratio converted into a digital value and that of an oscillating signal from an oscillator controlled by using the digital value in each cycle of a reference frequency, a data conversion unit that has a variable gain amplification unit to change a gain and causes output of the phase comparison unit to converge to an arbitrary setting value, an offset detection unit that detects an offset arising due to a change in gain of the variable gain amplification unit using output of the phase comparison unit, and an offset compensation unit that compensates for the offset detected by the offset detection unit in timing when the gain of the variable gain amplification unit changes.
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