Invention Application
- Patent Title: Test Pad Design for Reducing the Effect of Contact Resistances
- Patent Title (中): 用于降低接触电阻效应的测试垫设计
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Application No.: US12196531Application Date: 2008-08-22
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Publication No.: US20100045325A1Publication Date: 2010-02-25
- Inventor: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
- Applicant: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L23/50
Abstract:
An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
Public/Granted literature
- US07825678B2 Test pad design for reducing the effect of contact resistances Public/Granted day:2010-11-02
Information query
