发明申请
- 专利标题: Capacitor Die Design for Small Form Factors
- 专利标题(中): 小型电容器模具设计
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申请号: US12620884申请日: 2009-11-18
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公开(公告)号: US20100123215A1公开(公告)日: 2010-05-20
- 发明人: Yuancheng Christopher Pan , Fifin Sweeney , Charlie Paynter , Kevin R. Bowles , Jason R. Gonzalez
- 申请人: Yuancheng Christopher Pan , Fifin Sweeney , Charlie Paynter , Kevin R. Bowles , Jason R. Gonzalez
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM INCORPORATED
- 当前专利权人: QUALCOMM INCORPORATED
- 当前专利权人地址: US CA San Diego
- 主分类号: H01L23/52
- IPC分类号: H01L23/52 ; H01L21/50 ; H01L23/498
摘要:
A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.