公开(公告)号：US20100123215A1

公开(公告)日：2010-05-20

申请号：US12620884

申请日：2009-11-18

申请人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Charlie Paynter ,  Kevin R. Bowles ,  Jason R. Gonzalez

发明人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Charlie Paynter ,  Kevin R. Bowles ,  Jason R. Gonzalez

IPC分类号： H01L23/52 ,  H01L21/50 ,  H01L23/498

CPC分类号： H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5286 ,  H01L23/642 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.

摘要翻译： 半导体封装具有电容器裸片和封装衬底。 电容器管芯耦合到耦合到封装衬底的管芯的前侧或后侧上的电路，用于提供去耦电容。 在一个示例中，电容器裸片在包装阵列的填充区域中并且与封装阵列相邻的区域耦合到封装衬底的接地侧。 在另一示例中，电容器管芯可以堆叠在管芯上并且通过引线接合耦合到管芯上的电路。 电容器管芯降低了集成电路的阻抗，允许在较高频率下工作。

公开(公告)号：US20100327433A1

公开(公告)日：2010-12-30

申请号：US12491568

申请日：2009-06-25

申请人： Fifin Sweeney ,  Mario Francisco Velez ,  Yuancheng Christopher Pan ,  Shiqun Gu

发明人： Fifin Sweeney ,  Mario Francisco Velez ,  Yuancheng Christopher Pan ,  Shiqun Gu

IPC分类号： H01L23/34 ,  H01L23/02 ,  H01L21/00

CPC分类号： H01L23/642 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

摘要翻译： 集成电路封装包括去耦电容器。 集成电路封装还包括封装基板。 去耦电容器至少部分地嵌入在封装衬底中。 集成电路封装还包括安装到封装衬底的管芯。 管芯耦合到去耦电容器。 芯片从去耦电容器接收基本上瞬时的电流。

公开(公告)号：US09048112B2

公开(公告)日：2015-06-02

申请号：US12825937

申请日：2010-06-29

申请人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01R12/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/64 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/02 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02371 ,  H01L2224/05624 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/11 ,  H05K1/165 ,  H05K1/181 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

摘要翻译： 堆叠式集成电路包括第一层IC和第二层IC。 第一层IC和第二层IC的主动面相互面对。 互连结构，例如microbumps，将第一层IC耦合到第二层IC。 电压调节器的有源部分集成在第一半导体IC中并耦合到嵌入在其上安装有堆叠IC的封装衬底中的无源组件（例如，电容器或电感器）。 无源部件可以是在封装衬底中的多个通孔，为电压调节器的有源部分提供电感。 通过将封装衬底中的通孔耦合到安装有封装衬底的印刷电路板中的通孔，增加了提供给电压调节器的有源部分的电感。

公开(公告)号：US20110317387A1

公开(公告)日：2011-12-29

申请号：US12825937

申请日：2010-06-29

申请人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H05K7/06 ,  H01L23/48 ,  H01L29/92 ,  H01L29/86 ,  H01L25/16 ,  H01L21/50

CPC分类号： H01L23/5384 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/02 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02371 ,  H01L2224/05624 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/11 ,  H05K1/165 ,  H05K1/181 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

摘要翻译： 堆叠式集成电路包括第一层IC和第二层IC。 第一层IC和第二层IC的主动面相互面对。 互连结构，例如microbumps，将第一层IC耦合到第二层IC。 电压调节器的有源部分集成在第一半导体IC中并耦合到嵌入在其上安装有堆叠IC的封装衬底中的无源组件（例如，电容器或电感器）。 无源部件可以是在封装衬底中的多个通孔，为电压调节器的有源部分提供电感。 通过将封装衬底中的通孔耦合到安装有封装衬底的印刷电路板中的通孔，增加了提供给电压调节器的有源部分的电感。

公开(公告)号：US20120257618A1

公开(公告)日：2012-10-11

申请号：US13440805

申请日：2012-04-05

申请人： Yuancheng Christopher Pan ,  Tian Yu ,  Chongyang Wang ,  Chunxing Huang ,  Zhenhua Xu

发明人： Yuancheng Christopher Pan ,  Tian Yu ,  Chongyang Wang ,  Chunxing Huang ,  Zhenhua Xu

IPC分类号： H04L12/50 ,  H04L12/66

CPC分类号： H04L49/40 ,  H04L49/45

摘要： A system and method for expanding a chassis network using soft interconnects, including a hybrid chassis comprising a first fabric card comprising a first switching fabric, a second fabric card comprising a second switching fabric, a first set of line cards coupled to the first switching fabric via a first set of hard connections, and coupled to an interface associated with the second switching fabric via a soft connection, and a second set of line cards coupled to the second fabric card.

摘要翻译： 一种用于使用软互连来扩展机箱网络的系统和方法，包括混合机架，其包括包括第一交换结构的第一组织卡，包括第二交换结构的第二组织卡，耦合到所述第一交换结构的第一组线卡 经由第一组硬连接，并且经由软连接耦合到与所述第二交换结构相关联的接口，以及耦合到所述第二结构卡的第二组线卡。

公开(公告)号：US20110215863A1

公开(公告)日：2011-09-08

申请号：US13108335

申请日：2011-05-16

申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01L25/00

CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

摘要： A method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate and coupling the die to the at least one passive component. Mounting the active portion of the voltage regulator includes mounting the die on the packaging substrate where the die includes the active portion of the voltage regulator.

摘要翻译： 向安装在封装基板上的管芯提供电压的方法包括将电压调节器的有源部分安装在封装基板上。 该方法还包括将电压调节器的有源部分耦合到至少部分地嵌入封装衬底中的至少一个无源部件，并将管芯耦合到至少一个无源部件。 安装电压调节器的有源部分包括将管芯安装在封装衬底上，其中管芯包括电压调节器的有源部分。

公开(公告)号：US20120293972A1

公开(公告)日：2012-11-22

申请号：US13367932

申请日：2012-02-07

申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01L23/12 ,  H01L21/50

CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

摘要： A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

摘要翻译： 堆叠集成电路（IC）装置包括具有有源面的半导体IC和互连结构。 主动面从电压调节器（MEG）接收稳压电压。 将调节电压提供给半导体IC的VREG的有效部分耦合到互连结构。 包装衬底包括一个或多个包括第一组通孔的电感器。 第一组通孔耦合到互连结构并与有源部分配合以提供用于半导体IC的调节电压。 IC还包括耦合到封装衬底的印刷电路板（PCB）。 PCB包括耦合到第一组通孔的第二组通孔。 IC还包括PCB上的一个或多个导电路径。 导电路径将第二组通孔的至少两个通孔耦合在一起。

公开(公告)号：US20110050334A1

公开(公告)日：2011-03-03

申请号：US12552321

申请日：2009-09-02

申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01L25/00

CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

摘要： A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.

摘要翻译： 半导体封装系统具有其中部分或完全嵌入电感器和/或电容器的封装衬底。 电压调节器的有源部分安装在封装基板上，并将稳定的电压提供给也安装在封装基板上的管芯。 或者，电压调节器的有源部分集成到管芯中，电压调节器将电压提供给。 电压调节器与电感器和/或电容器配合以向模具提供电压。 电感器可以穿过封装衬底中的通孔。 对于额外的电感，通过安装封装衬底的印刷电路板中的通孔可以耦合到封装衬底中的通孔。

公开(公告)号：US08692368B2

公开(公告)日：2014-04-08

申请号：US13367932

申请日：2012-02-07

申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC分类号： H01L23/34

CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

摘要： A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

摘要翻译： 堆叠集成电路（IC）装置包括具有有源面的半导体IC和互连结构。 主动面从电压调节器（MEG）接收稳压电压。 将调节电压提供给半导体IC的VREG的有效部分耦合到互连结构。 包装衬底包括一个或多个包括第一组通孔的电感器。 第一组通孔耦合到互连结构并与有源部分配合以提供用于半导体IC的调节电压。 IC还包括耦合到封装基板的印刷电路板（PCB）。 PCB包括耦合到第一组通孔的第二组通孔。 IC还包括PCB上的一个或多个导电路径。 导电路径将第二组通孔的至少两个通孔耦合在一起。