发明申请
- 专利标题: TIME-TO-DIGITAL CONVERTER AND ALL-DIGITAL PHASE-LOCKED LOOP
- 专利标题(中): 时间到数字转换器和全数字锁相环
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申请号: US12627229申请日: 2009-11-30
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公开(公告)号: US20100134165A1公开(公告)日: 2010-06-03
- 发明人: Do-hwan OH , Kyo-Jin CHOO , Deog-Kyoon JEONG
- 申请人: Do-hwan OH , Kyo-Jin CHOO , Deog-Kyoon JEONG
- 申请人地址: KR Suwon-si KR Seoul
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.,SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.,SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- 当前专利权人地址: KR Suwon-si KR Seoul
- 优先权: KR10-2009-0076780 20090819
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; H03K5/13
摘要:
A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.
公开/授权文献
- US07973578B2 Time-to-digital converter and all-digital phase-locked loop 公开/授权日:2011-07-05
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