利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2 条记录 (耗时 0.018 秒)

    ADJUSTABLE CAPACITOR, DIGITALLY CONTROLLED OSCILLATOR, AND ALL-DIGITAL PHASE LOCKED LOOP
    1.
    发明申请
    ADJUSTABLE CAPACITOR, DIGITALLY CONTROLLED OSCILLATOR, AND ALL-DIGITAL PHASE LOCKED LOOP 有权
    可调节电容器，数字控制振荡器和全数字锁相环

    公开(公告)号：US20100156550A1

    公开(公告)日：2010-06-24

    申请号：US12630885

    申请日：2009-12-04

    申请人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

    发明人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

    IPC分类号： H03L7/02 ,  H01G4/40

    CPC分类号： H03L7/099 ,  H03J2200/10 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/50

    摘要： An adjustable capacitor is provided including a capacitor unit including a plurality of capacitor groups aligned in a matrix format and a switch unit to adjust capacitance by connecting the plurality of capacitor groups in parallel according to a selection signal of a column and row of the matrix. Accordingly, the adjustable capacitor may be realized of a small size but with a high capacitance change rate.

    摘要翻译： 提供了一种可调节电容器，包括：电容器单元，其包括以矩阵形式排列的多个电容器组;以及开关单元，用于根据矩阵的列和行的选择信号并联连接多个电容器组来调整电容。 因此，可调电容器可以实现为小尺寸但具有高电容变化率。

    TIME-TO-DIGITAL CONVERTER AND ALL-DIGITAL PHASE-LOCKED LOOP
    2.
    发明申请
    TIME-TO-DIGITAL CONVERTER AND ALL-DIGITAL PHASE-LOCKED LOOP 有权
    时间到数字转换器和全数字锁相环

    公开(公告)号：US20100134165A1

    公开(公告)日：2010-06-03

    申请号：US12627229

    申请日：2009-11-30

    申请人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

    发明人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

    IPC分类号： H03L7/06 ,  H03K5/13

    CPC分类号： G04F10/005 ,  G04F10/06 ,  H03L7/087 ,  H03L7/091

    摘要： A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.

    摘要翻译： 时间数字转换器（TDC）包括接收第一信号和第二信号的转换器，使用串联耦合的多个延迟元件来相位延迟第二信号，将延迟的第二信号与第一信号进行比较 并且输出相对于第一信号的第二信号的相位误差，接收第一信号的相位频率检测器和来自多个延迟元件中的一个节点的第三信号，并且输出第二信号之间的相位差 第一信号和第三信号，以及频率检测器，其使用相位频率检测器和第二信号的输出信号将相对于第一信号的第二信号的频率误差作为数字码输出。