发明申请
- 专利标题： Semiconductor Device with Reduced Parasitic Inductance
- 专利标题（中）： 具有降低寄生电感的半导体器件
-
申请号： US12721201申请日： 2010-03-10
-
公开(公告)号： US20100176430A1公开(公告)日： 2010-07-15
- 发明人: Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
- 申请人： Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 优先权： JP2006-149489 20060530
- 主分类号： H01L27/06
- IPC分类号： H01L27/06
摘要：
The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are
公开/授权文献
信息查询
IPC分类:
