公开(公告)号：US20150303288A1

公开(公告)日：2015-10-22

申请号：US14418610

申请日：2012-09-07

申请人： Takayuki HASHIMOTO ,  Mutsuhiro MORI ,  Masahiro MASUNAGA

发明人： Takayuki HASHIMOTO ,  Mutsuhiro MORI ,  Masahiro MASUNAGA

IPC分类号： H01L29/739 ,  H02M7/537

CPC分类号： H02M1/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1079 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7394 ,  H01L29/7396 ,  H01L29/7397 ,  H02M1/08 ,  H02M7/003 ,  H02M7/537 ,  H02M7/5387 ,  H02M2001/0054

摘要： The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

摘要翻译： 本发明提供一种用于功率转换的开关装置（100），其中具有n型发射极区（3）的第一栅电极（6），p型沟道层（2），第二栅电极（13） ，并且在n型半导体衬底（1）的表面侧依次重复布置p型浮动层（15）。 夹着p型沟道层（2）的两个栅极（6,13）之间的间隔a被配置为小于夹着p型浮动层的两个栅极（13,6）之间的间隔b 15）。 第一栅电极（6）和第二栅电极（13）都被提供有驱动定时具有时差的驱动信号。

公开(公告)号：US08618632B2

公开(公告)日：2013-12-31

申请号：US13041778

申请日：2011-03-07

申请人： Tetsuya Kawashima ,  Takayuki Hashimoto

发明人： Tetsuya Kawashima ,  Takayuki Hashimoto

IPC分类号： H01L23/52 ,  H05K1/14

CPC分类号： H01L27/0694 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/642 ,  H01L25/16 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/0213 ,  H05K1/113 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a semiconductor device in which a wiring inductance of a DC/DC converter formed on a multi-layered wiring substrate can be reduced and the characteristics can be improved. In the semiconductor device, in an input-side capacitor, one capacitor electrode is electrically connected to a power-supply pattern between a control power MOSFET and a synchronous power MOSFET, and the other capacitor electrode is electrically connected to a ground pattern therebetween. The multi-layered wiring substrate includes: a via conductor arranged at a position of the one capacitor electrode for electrically connecting among a plurality of power-supply patterns in a thickness direction; and a via conductor arranged at a position of the other capacitor electrode for electrically connecting among a plurality of ground patterns in a thickness direction.

摘要翻译： 提供一种半导体器件，其中可以减少形成在多层布线基板上的DC / DC转换器的布线电感并且可以提高特性。 在半导体装置中，在输入侧电容器中，一个电容电极电连接到控制功率MOSFET与同步功率MOSFET之间的电源图案，另一个电容电极与它们之间的接地图电连接。 所述多层布线基板包括：通孔导体，布置在所述一个电容器电极的位置，用于在多个电源图案之间沿厚度方向电连接; 以及布置在另一电容电极的位置处的通孔导体，用于在多个接地图案之间沿厚度方向电连接。

公开(公告)号：US08319289B2

公开(公告)日：2012-11-27

申请号：US12005918

申请日：2007-12-27

申请人： Masaki Shiraishi ,  Noboru Akiyama ,  Takayuki Hashimoto

发明人： Masaki Shiraishi ,  Noboru Akiyama ,  Takayuki Hashimoto

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7816 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66689

摘要： A technique for suppressing lowering of withstand voltage and lowering of breakdown resistance and reducing a feedback capacitance of a power MISFET is provided. A lateral power MISFET that comprises a trench region whose insulating layer is formed shallower than an HV-Nwell layer is provided in the HV-Nwell layer (drift region) formed on a main surface of a semiconductor substrate in a direction from the main surface to the inside. The lateral power MISFET has an arrangement on a plane of the main surface including a source layer (source region) and a drain layer (drain region) arranged at opposite sides to each other across a gate electrode (first conducting layer), and a dummy gate electrode (second conducting layer) that is different from the gate electrode is arranged between the gate electrode and the drain layer.

摘要翻译： 提供了用于抑制耐压降低和击穿电阻降低并降低功率MISFET的反馈电容的技术。 在半导体衬底的主表面上形成的HV-Nwell层（漂移区域）中，沿着从主表面到主体表面的方向，设置包括其绝缘层形成为比HV-Nwell层浅的沟槽区域的横向功率MISFET 里面。 横向功率MISFET具有在主表面的平面上的布置，包括在栅极电极（第一导电层）上彼此相对设置的源极层（源极区域）和漏极层（漏极区域） 与栅电极不同的栅电极（第二导电层）配置在栅电极和漏极层之间。

公开(公告)号：US08258711B2

公开(公告)日：2012-09-04

申请号：US12779343

申请日：2010-05-13

申请人： Noboru Akiyama ,  Takayuki Hashimoto ,  Takashi Hirao ,  Nobuyoshi Matsuura ,  Hideo Ishii

发明人： Noboru Akiyama ,  Takayuki Hashimoto ,  Takashi Hirao ,  Nobuyoshi Matsuura ,  Hideo Ishii

IPC分类号： H05B37/02

CPC分类号： H01L29/7813 ,  G09G3/342 ,  G09G2320/064 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/41766 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7815 ,  H05B33/0818 ,  H05B33/0827 ,  H05B33/089 ,  Y02B20/347

摘要： The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.

摘要翻译： 半导体器件包括在驱动LED阵列（串联数字×并联数n）的LED驱动电路（电流调节器）中，并且由多个（n个）LED驱动装置形成， 在每个串中流动的电流（恒流驱动）。 使用垂直半导体器件，例如垂直MOSFET作为LED驱动器件。 作为恒流驱动装置的主装置和在调光期间用作断路开关的辅助装置都形成在由垂直半导体装置形成的装置的芯片的内部。 在装置的第一表面中，主装置和附属装置的每个源区形成为通过隔离区彼此绝缘。

公开(公告)号：US20120217577A1

公开(公告)日：2012-08-30

申请号：US13402973

申请日：2012-02-23

申请人： Takayuki HASHIMOTO ,  Masahiro Masunaga

发明人： Takayuki HASHIMOTO ,  Masahiro Masunaga

IPC分类号： H01L29/78

CPC分类号： H01L29/66727 ,  H01L21/2257 ,  H01L27/0922 ,  H01L29/0856 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

摘要： A trench-gate vertical-channel type power MOSFET has an advantage of a low on-state resistance. With increasing miniaturization, fluctuations in on-state resistance have posed a problem. In addition, a structural limitation in miniaturization also has posed a problem. These problems are not only those of a single power MOSFET but also are important ones in integrated circuit devices, such as IGBT using a similar structure, obtained by integrating CMOS and such a power active device on a single chip. The invention provides a semiconductor device having a trench-gate vertical-channel type power active device, such as trench-gate vertical-channel type power MOSFET, in which the width of the interlayer insulating film is made almost equal to that of the trench and a portion of the source region is comprised of a polysilicon member.

摘要翻译： 沟槽栅极垂直沟道型功率MOSFET具有低导通状态电阻的优点。 随着小型化的加剧，导通电阻的波动也带来了一个问题。 另外，小型化的结构限制也带来了问题。 这些问题不仅仅是单功率MOSFET的问题，而且在集成电路器件中也是重要的，例如通过在单个芯片上集成CMOS和这种功率有源器件获得的类似结构的IGBT。 本发明提供一种半导体器件，其具有沟槽栅极垂直沟道型功率有源器件，例如沟槽栅极垂直沟道型功率MOSFET，其中层间绝缘膜的宽度大致等于沟槽的宽度， 源极区的一部分由多晶硅构件构成。

公开(公告)号：US08203380B2

公开(公告)日：2012-06-19

申请号：US12483668

申请日：2009-06-12

申请人： Takayuki Hashimoto ,  Takashi Hirao ,  Noboru Akiyama

发明人： Takayuki Hashimoto ,  Takashi Hirao ,  Noboru Akiyama

IPC分类号： H01L25/00

CPC分类号： H01L27/0629 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

摘要： In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.

摘要翻译： 在半导体装置中，高侧驱动器配置在比高侧开关更靠近半导体基板的周围的区域，低边驱动器配置在比半导体基板的周边更靠近的区域， 低端开关。 通过这种方式，经由高侧开关和低侧开关从输入电容器的正极端子到输入电容器的负极端子的路径很短，从驱动电容器的正极端子到负极的路径 通过低侧驱动器的驱动电容器的端子短，通过高侧驱动器从引导电容器的正极端子到引导电容器的负极端子的路径短，因此，寄生电感 可以降低转换效率。

公开(公告)号：US20120001609A1

公开(公告)日：2012-01-05

申请号：US13230947

申请日：2011-09-13

申请人： Masaki SHIRAISHI ,  Takayuki Hashimoto ,  Noboru Akiyama

发明人： Masaki SHIRAISHI ,  Takayuki Hashimoto ,  Noboru Akiyama

IPC分类号： G05F1/46

CPC分类号： H02M1/08 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H03K17/0822 ,  H03K17/165 ,  H03K17/166 ,  H03K17/6871 ,  H01L2924/00 ,  H01L2224/45099

摘要： In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.

摘要翻译： 在非隔离型DC / DC转换器中，从通过高侧MOSFET的主电路以外的部分施加驱动低侧MOSFET的栅极的低侧预驱动器的基准电位， 低侧MOSFET，使得低侧MOSFET的源极与预驱动器之间的寄生电感增加，而不增加主电路中的寄生电感的和，并且低侧MOSFET的栅极的负电位驱动 并且可以防止在不添加任何构件和改变驱动系统的情况下自启闭现象。

公开(公告)号：US20110278655A1

公开(公告)日：2011-11-17

申请号：US13192584

申请日：2011-07-28

申请人： Takayuki Hashimoto ,  Noboru Akiyama ,  Masaki Shiraishi ,  Tetsuya Kawashima

发明人： Takayuki Hashimoto ,  Noboru Akiyama ,  Masaki Shiraishi ,  Tetsuya Kawashima

IPC分类号： H01L27/06

CPC分类号： H01L25/16 ,  G06F1/26 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.

摘要翻译： 降低了电源单元主电路的寄生电感。 在具有用于高侧开关的功率MOSFET和低侧开关的功率MOSFET串联的电路的非绝缘DC-DC转换器中，用于高侧开关的功率MOSFET和用于低侧开关的功率MOSFET是 由n沟道垂直MOSFET形成，并且用于高侧开关的功率MOSFET的源极和用于低侧开关的功率MOSFET的漏电极经由相同的管芯焊盘电连接。

公开(公告)号：US20110227069A1

公开(公告)日：2011-09-22

申请号：US13048938

申请日：2011-03-16

申请人： Takayuki HASHIMOTO

发明人： Takayuki HASHIMOTO

IPC分类号： H01L23/58

CPC分类号： H01L25/162 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L27/0629 ,  H01L29/7397 ,  H01L29/861 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

摘要翻译： 提供了能够检测诸如沟槽栅型MOSFET的小型化MOSFET中的MOSFET的工作电流和二极管电流的半导体衬底。 半导体衬底包括主电流区域和电流感测区域，其中流过主电流区域的主电流的电流小于该电流区域。 主电流区域具有设置在主表面上的源电极，源电极与p型半导体区域（主体）和n +型半导体区域（源极）接触，并且电流感测区域具有MOSFET电流 检测电极和主表面上的二极管电流检测电极，MOSFET电流检测电极与p型半导体区域（主体）和n +型半导体区域（源极）接触，二极管电流检测电极接触 与p型半导体区域（主体）。

公开(公告)号：US20110220979A1

公开(公告)日：2011-09-15

申请号：US13041778

申请日：2011-03-07

申请人： Tetsuya KAWASHIMA ,  Takayuki HASHIMOTO

发明人： Tetsuya KAWASHIMA ,  Takayuki HASHIMOTO

IPC分类号： H01L27/06

CPC分类号： H01L27/0694 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/642 ,  H01L25/16 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/0213 ,  H05K1/113 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a semiconductor device in which a wiring inductance of a DC/DC converter formed on a multi-layered wiring substrate can be reduced and the characteristics can be improved. In the semiconductor device, in an input-side capacitor, one capacitor electrode is electrically connected to a power-supply pattern between a control power MOSFET and a synchronous power MOSFET, and the other capacitor electrode is electrically connected to a ground pattern therebetween. The multi-layered wiring substrate includes: a via conductor arranged at a position of the one capacitor electrode for electrically connecting among a plurality of power-supply patterns in a thickness direction; and a via conductor arranged at a position of the other capacitor electrode for electrically connecting among a plurality of ground patterns in a thickness direction.

摘要翻译： 提供一种半导体器件，其中可以减少形成在多层布线基板上的DC / DC转换器的布线电感并且可以提高特性。 在半导体装置中，在输入侧电容器中，一个电容电极电连接到控制功率MOSFET与同步功率MOSFET之间的电源图案，另一个电容电极与它们之间的接地图电连接。 所述多层布线基板包括：通孔导体，布置在所述一个电容器电极的位置，用于在多个电源图案之间沿厚度方向电连接; 以及布置在另一电容电极的位置处的通孔导体，用于在多个接地图案之间沿厚度方向电连接。