发明申请
- 专利标题： METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM
- 专利标题（中）： 制造半导体器件的方法，其能够抑制由形成绝缘膜形成的掺杂通道区域中的浓度浓度降低
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申请号： US12754097申请日： 2010-04-05
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公开(公告)号： US20100190306A1公开(公告)日： 2010-07-29
- 发明人: Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
- 申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 优先权： JP2003-143438 20030521
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L21/02
摘要：
A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
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