-
1.发明申请Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film 有权制造半导体器件的方法，该半导体器件能够抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低公开(公告)号：US20060079061A1
公开(公告)日：2006-04-13
申请号：US11292360
申请日：2005-12-02
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1(W2/T)
摘要翻译： 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成氧化硅膜（20）和氮化硅膜（21）的情况下，将p型杂质离子（23×23×23×2×××××××××××××） 方向从对角线上方。 对于离子注入的注入角度α，采用满足关系tanθ-1（W 2 / T）<α<= TAN 的注入角度 （W 1 / T），其中W 1是第一部分（21 <1> 1）与第四部分（21 <4>）之间的间隔，第三部分 （21,33）和第六部分（21×6）; W 2是第二部分（21 ... 2）与第五部分（21 ... 5）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。 当将注入角度α控制在该范围内时，将杂质离子（23,23,23）注入到第二侧表面（10 A 2 / SUB>）和通过氧化硅膜（13）的第五侧表面（10 A 5 S）。
-
2.发明授权Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film 有权制造半导体器件的方法，该半导体器件能够抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低公开(公告)号：US07244655B2
公开(公告)日：2007-07-17
申请号：US11292360
申请日：2005-12-02
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1(W2/T)
摘要翻译： 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成氧化硅膜（20）和氮化硅膜（21）的情况下，将p型杂质离子（23×23×23×2×××××××××××××） 方向从对角线上方。 对于离子注入的注入角度α，采用满足关系tanθ-1（W 2 / T）<α<= TAN 的注入角度 （W 1 / T），其中W 1是第一部分（21 <1> 1）与第四部分（21 <4>）之间的间隔，第三部分 （21,33）和第六部分（21×6）; W 2是第二部分（21 ... 2）与第五部分（21 ... 5）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。 当将注入角度α控制在该范围内时，将杂质离子（23,23,23）注入到第二侧表面（10 A 2 / SUB>）和通过氧化硅膜（13）的第五侧表面（10 A 5 S）。
-
3.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM 审中-公开制造半导体器件的方法，其能够抑制由形成绝缘膜形成的掺杂通道区域中的浓度浓度降低公开(公告)号：US20100190306A1
公开(公告)日：2010-07-29
申请号：US12754097
申请日：2010-04-05
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译： 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成氧化硅膜和氮化硅膜的情况下，在对角上方沿Y方向注入p型杂质离子。 对于离子注入的注入角度α，采用满足关系tan-1（W2 / T）<α＆nlE; tan-1（W1 / T）的植入角度，其中W1是第一部分和 第四部分和第三部分和第六部分之间的间隔; W2是第二部分和第五部分之间的间隔; T是氧化硅膜和氮化硅膜的总膜厚。 当将注入角度α控制在该范围内时，杂质离子通过氧化硅膜注入第二侧表面和第五侧表面。
-
公开(公告)号：US06998319B2
公开(公告)日：2006-02-14
申请号：US10730099
申请日：2003-12-09
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1(W2/T)
-
5.发明授权Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film 失效制造半导体器件的方法，该半导体器件能够抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低公开(公告)号：US07691713B2
公开(公告)日：2010-04-06
申请号：US11767734
申请日：2007-06-25
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译： 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成氧化硅膜（20）和氮化硅膜（21）的情况下，沿着Y方向从对角线上方注入p型杂质离子（23,23,2）。 至于植入角度。 采用满足关系tan-1（W2 / T）<α＆nlE; tan-1（W1 / T）的植入角度，其中W1是第一部分（211）和第四部分 （214）和第三部分（213）和第六部分（216）之间的间隔; W2是第二部分（212）和第五部分（215）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。 当将注入角度α控制在该范围内时，杂质离子（231,231）通过氧化硅膜（13）注入第二侧面（10A2）和第五侧面（10A5）。
-
6.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULTING FILM 失效制造半导体器件的方法，其能够抑制由形成绝缘膜形成的掺杂通道区域中的浓度浓度降低公开(公告)号：US20070243687A1
公开(公告)日：2007-10-18
申请号：US11767734
申请日：2007-06-25
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译： 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成有氧化硅膜（20）和氮化硅膜（21）的情况下，将p型杂质离子（23,2,2,3 ...）从对角线方向注入Y方向。 至于植入角度。 的离子注入，采用满足tan <-1≤（W 2 / T）<α<= TAN-1（W 1 / T）的关系的注入角度 ，其中W 1是第一部分（21 <1> 1）和第四部分（21 <4>）之间的间隔，以及第三部分（21,33）之间的间隔 ）和第六部分（21×6）; W 2是第二部分（21 ... 2）与第五部分（21 ... 5）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。 当将注入角度α控制在该范围内时，杂质离子（23×1，23×1）被注入到第二侧表面（10A / SUB>）和通过氧化硅膜（13）的第五侧表面（10 A 5 S）。
-
公开(公告)号：US06483192B1
公开(公告)日：2002-11-19
申请号：US09588479
申请日：2000-06-07
申请人： Heiji Kobayashi
发明人： Heiji Kobayashi
IPC分类号： H01L2328
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A pad is formed on a substrate with a pad formed to approximate to the wire. Silicon oxide films are formed to cover the wire and the pad. A contact hole is formed through the silicon oxide films. A side wall oxide film is formed on the side surface and the bottom surface of the contact hole except an exposed surface of the pad. A conductive layer is formed to be electrically connected with the pad. When the contact hole is formed to overlap with the wire and the pad by misalignment or the like, the side wall oxide film electrically insulates the conductive layer and the wire from each other, thereby preventing electrical shorting and obtaining a semiconductor device attaining high integration and refinement.
摘要翻译： 衬垫形成在衬底上，衬垫形成为接近线。 形成氧化硅膜以覆盖电线和焊盘。 通过氧化硅膜形成接触孔。 除了焊盘的暴露表面之外，在接触孔的侧表面和底表面上形成侧壁氧化膜。 导电层形成为与焊盘电连接。 当接触孔通过不对准等形成为与导线和焊盘重叠时，侧壁氧化膜使导电层和电线彼此电绝缘，从而防止电短路并获得获得高集成度的半导体器件， 细化。
-
公开(公告)号：US06864580B2
公开(公告)日：2005-03-08
申请号：US09915567
申请日：2001-07-27
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L23/48 , H01L21/4763 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76897 , H01L21/76831
摘要： A semiconductor device having a structure in which no short circuit occurs between plug interconnections even when a void occurs in an insulating layer in a gap between wiring layers and a method of manufacturing the same are attained. The method includes: a step of forming transfer gates so as to be close to each other with a gap on a semiconductor substrate; a step of burying the gap and covering a wiring layer; a step of opening a contact hole in an insulating layer in the gap portion; a step of depositing a short-circuit preventing insulating film in the contact hole; an etch back step of removing the short-circuit preventing insulating film at least on the bottom of the gap to expose the semiconductor substrate; and a step of forming a plug interconnection.
摘要翻译： 即使在布线层之间的间隙中的绝缘层中发生空隙的情况下也可以获得其插塞互连之间不发生短路的结构及其制造方法。 该方法包括：在半导体衬底上以间隙形成彼此靠近的传输栅极的步骤; 埋置间隙并覆盖布线层的步骤; 在间隙部分中的绝缘层中打开接触孔的步骤; 在接触孔中沉积短路防止绝缘膜的步骤; 至少在所述间隙的底部去除所述短路防止绝缘膜以露出所述半导体衬底的回蚀步骤; 以及形成插头互连的步骤。
-
公开(公告)号：US08846485B2
公开(公告)日：2014-09-30
申请号：US12837449
申请日：2010-07-15
申请人： Heiji Kobayashi , Yukihiro Nagai
发明人： Heiji Kobayashi , Yukihiro Nagai
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings. A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased.
摘要翻译： 提供一种用于制造动态随机存取存储器的电容器底部电极的方法。 该方法包括提供具有存储单元区域并在衬底的存储单元区域上形成多晶硅模板层的衬底。 在多晶硅模板层上形成支撑层，并且穿过支撑层和多晶硅模板层形成多个开口，并且在由开口暴露的多晶硅模板层的至少一部分上形成衬垫层。 在基板上形成基本上与基板共形的导电层。 去除支撑层上的导电层的一部分以形成多个电容器底部电极。 使用多晶硅模板层，形成具有相对更好的轮廓的开口，并且可以减小装置的尺寸。
-
公开(公告)号：US20120018801A1
公开(公告)日：2012-01-26
申请号：US12839412
申请日：2010-07-20
申请人： Heiji Kobayashi , Yukihiro Nagai
发明人： Heiji Kobayashi , Yukihiro Nagai
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L21/762 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
摘要翻译： 垂直沟道晶体管阵列具有由多个半导体柱形成的有源区。 多个嵌入式位线平行布置在半导体衬底中并沿列方向延伸。 多个位线触点分别设置在一个嵌入位线的一侧。 多个嵌入字线平行地布置在嵌入式位线上方并沿行方向延伸。 此外，嵌入字线将同一行中的半导体柱与夹在嵌入字线和半导体柱之间的栅介质层连接。 电流泄漏隔离结构设置在嵌入式位线的端子处，以防止相邻位线触点之间的电流泄漏。
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.017 秒)