A method for making an integrated circuit device by: forming a plurality of transistors on a semiconductor substrate; forming multilayer interconnects by depositing a layer of metal; patterning the metal layer; depositing a first dielectric material, depositing a second dielectric material, patterning the first and second dielectric materials; and depositing a via filling metal material into the patterned areas; or, alternatively, by forming transistors on a substrate; depositing one of an electrically insulating or electrically conducting material; patterning said one of an electrically insulating or electrically conducting material; and depositing the other of the electrically insulating or electrically conducting material, so as to form a layer over said transistors having both electrically insulating and electrically conducting portions; wherein the first dielectric material, which is an organosiloxane material, and the electrically insulating material each has a carbon to silicon ratio of 1.5 to 1 or more.