公开(公告)号：US20100317179A1

公开(公告)日：2010-12-16

申请号：US12382419

申请日：2009-03-16

申请人： Juha T. RANTALA ,  Jyri PAULASAARI ,  Janne KYLMA ,  Turo T. TORMANEN ,  Jarkko PIETIKAINEN ,  Nigel HACKER ,  Admir HADZIC

发明人： Juha T. RANTALA ,  Jyri PAULASAARI ,  Janne KYLMA ,  Turo T. TORMANEN ,  Jarkko PIETIKAINEN ,  Nigel HACKER ,  Admir HADZIC

IPC分类号： H01L21/28 ,  H01L21/768

CPC分类号： C09D183/14 ,  C08G77/50 ,  H01B3/46 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/76822 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31663 ,  H01L2924/00

摘要： A method for making an integrated circuit device by: forming a plurality of transistors on a semiconductor substrate; forming multilayer interconnects by depositing a layer of metal; patterning the metal layer; depositing a first dielectric material, depositing a second dielectric material, patterning the first and second dielectric materials; and depositing a via filling metal material into the patterned areas; or, alternatively, by forming transistors on a substrate; depositing one of an electrically insulating or electrically conducting material; patterning said one of an electrically insulating or electrically conducting material; and depositing the other of the electrically insulating or electrically conducting material, so as to form a layer over said transistors having both electrically insulating and electrically conducting portions; wherein the first dielectric material, which is an organosiloxane material, and the electrically insulating material each has a carbon to silicon ratio of 1.5 to 1 or more.

摘要翻译： 一种制造集成电路器件的方法，包括：在半导体衬底上形成多个晶体管; 通过沉积一层金属形成多层互连; 图案化金属层; 沉积第一电介质材料，沉积第二介电材料，图案化第一和第二电介质材料; 以及将通孔填充金属材料沉积到图案化区域中; 或者，通过在衬底上形成晶体管; 沉积电绝缘或导电材料之一; 图案化所述电绝缘或导电材料之一; 以及沉积所述电绝缘或导电材料中的另一个，以便在所述晶体管上形成具有电绝缘和导电部分的层; 其中作为有机硅氧烷材料的第一介电材料和电绝缘材料各自具有1.5至1或更大的碳硅比。