Invention Application
US20110018107A1 TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices 审中-公开
TSVS具有化学暴露的集成电路器件的TSV提示

TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices
Abstract:
A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
Information query
Patent Agency Ranking
0/0