发明申请
- 专利标题: Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
- 专利标题(中): 超大型集成电路的精确寄生电容提取
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申请号: US12893870申请日: 2010-09-29
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公开(公告)号: US20110023003A1公开(公告)日: 2011-01-27
- 发明人: Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
- 申请人: Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
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