发明申请
US20110023003A1 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
超大型集成电路的精确寄生电容提取

Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
摘要:
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
信息查询
0/0