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    Accurate parasitic capacitance extraction for ultra large scale integrated circuits
    1.
    发明授权
    Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
    超大规模集成电路的精确寄生电容提取

    公开(公告)号：US08214784B2

    公开(公告)日：2012-07-03

    申请号：US12893870

    申请日：2010-09-29

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
    2.
    发明申请
    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
    超大型集成电路的精确寄生电容提取

    公开(公告)号：US20110023003A1

    公开(公告)日：2011-01-27

    申请号：US12893870

    申请日：2010-09-29

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

    Accurate parasitic capacitance extraction for ultra large scale integrated circuits
    3.
    发明授权
    Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
    超大规模集成电路的精确寄生电容提取

    公开(公告)号：US07818698B2

    公开(公告)日：2010-10-19

    申请号：US11865304

    申请日：2007-10-01

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
    4.
    发明申请
    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
    超大型集成电路的精确寄生电容提取

    公开(公告)号：US20120260225A1

    公开(公告)日：2012-10-11

    申请号：US13527096

    申请日：2012-06-19

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
    5.
    发明申请
    Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
    超大型集成电路的精确寄生电容提取

    公开(公告)号：US20090007035A1

    公开(公告)日：2009-01-01

    申请号：US11865304

    申请日：2007-10-01

    申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

    摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

    IC design flow enhancement with CMP simulation
    6.
    发明授权
    IC design flow enhancement with CMP simulation 有权
    IC设计流程增强与CMP模拟

    公开(公告)号：US08336002B2

    公开(公告)日：2012-12-18

    申请号：US11688654

    申请日：2007-03-20

    申请人： Gwan Sin Chang ,  Yi-Kan Cheng ,  Ivy Chiu ,  Ke-Ying Su

    发明人： Gwan Sin Chang ,  Yi-Kan Cheng ,  Ivy Chiu ,  Ke-Ying Su

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F17/5031 ,  G06F2217/12 ,  Y02P90/265

    摘要： An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.

    摘要翻译： 集成电路（IC）设计方法包括提供IC设计布局数据; 基于IC设计布局模拟化学机械抛光（CMP）工艺到材料层，以产生各种几何参数; 根据CMP工艺仿真的各种几何参数提取电阻和电容; 并且基于所提取的电阻和电容来执行电路定时分析。

    IC Design Flow Enhancement With CMP Simulation
    7.
    发明申请
    IC Design Flow Enhancement With CMP Simulation 有权
    IC设计流程增强与CMP模拟

    公开(公告)号：US20070266356A1

    公开(公告)日：2007-11-15

    申请号：US11688654

    申请日：2007-03-20

    申请人： Gwan Sin Chang ,  Yi-Kan Cheng ,  Ivy Chiu ,  Ke-Ying Su

    发明人： Gwan Sin Chang ,  Yi-Kan Cheng ,  Ivy Chiu ,  Ke-Ying Su

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F17/5031 ,  G06F2217/12 ,  Y02P90/265

    摘要： An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.

    摘要翻译： 集成电路（IC）设计方法包括提供IC设计布局数据; 基于IC设计布局模拟化学机械抛光（CMP）工艺到材料层，以产生各种几何参数; 根据CMP工艺仿真的各种几何参数提取电阻和电容; 并且基于所提取的电阻和电容来执行电路定时分析。

    Performance-Aware Logic Operations for Generating Masks
    9.
    发明申请
    Performance-Aware Logic Operations for Generating Masks 有权
    用于生成面具的性能感知逻辑操作

    公开(公告)号：US20120043618A1

    公开(公告)日：2012-02-23

    申请号：US13284594

    申请日：2011-10-28

    申请人： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    发明人： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    IPC分类号： H01L27/092

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

    摘要翻译： 通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。 因此，可以在不违反设计规则的情况下改善两种装置的应力性能。