发明申请
US20110055668A1 METHOD, DEVICE, AND DIGITAL CIRCUITY FOR PROVIDING A CLOSED-FORM SOLUTION TO A SCALED ERROR LOCATOR POLYNOMIAL USED IN BCH DECODING 有权
用于向BCH解码中使用的缩放误差定位器多项式提供封闭形式解决方案的方法,设备和数字电路

METHOD, DEVICE, AND DIGITAL CIRCUITY FOR PROVIDING A CLOSED-FORM SOLUTION TO A SCALED ERROR LOCATOR POLYNOMIAL USED IN BCH DECODING
摘要:
A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH decoder device that can implement the method and a digital circuit that preserves operations implementing the method are also disclosed.
信息查询
0/0