发明申请
- 专利标题: IMPEDANCE OPTIMIZED CHIP SYSTEM
- 专利标题(中): 阻抗优化芯片系统
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申请号: US12757466申请日: 2010-04-09
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公开(公告)号: US20110057302A1公开(公告)日: 2011-03-10
- 发明人: James Raymond Spehar , Christian Paquet , Wayne A. Nunn , Dominicus M. Roozeboom , Joseph E. Schulze , Fatha Khalsa
- 申请人: James Raymond Spehar , Christian Paquet , Wayne A. Nunn , Dominicus M. Roozeboom , Joseph E. Schulze , Fatha Khalsa
- 申请人地址: NL Eindhoven
- 专利权人: NXP B.V
- 当前专利权人: NXP B.V
- 当前专利权人地址: NL Eindhoven
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L23/538 ; G06F17/50
摘要:
A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.
公开/授权文献
- US08482114B2 Impedance optimized chip system 公开/授权日:2013-07-09
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