公开(公告)号：US20110057302A1

公开(公告)日：2011-03-10

申请号：US12757466

申请日：2010-04-09

申请人： James Raymond Spehar ,  Christian Paquet ,  Wayne A. Nunn ,  Dominicus M. Roozeboom ,  Joseph E. Schulze ,  Fatha Khalsa

发明人： James Raymond Spehar ,  Christian Paquet ,  Wayne A. Nunn ,  Dominicus M. Roozeboom ,  Joseph E. Schulze ,  Fatha Khalsa

IPC分类号： H01L23/498 ,  H01L23/538 ,  G06F17/50

CPC分类号： G06F17/5045 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/48011 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

摘要翻译： 高带宽电路被分割成多个部分，每个部分用于在对应的半导体芯片上实现，产生用于每个相应芯片的一个或多个管芯焊盘的布置，并且产生用于每个相应芯片的芯片位置，给定 产生封装和给定的封装I / O布置，芯片键合布置的产生和芯片位置相对于给定的芯片封装参数，并且被产生以建立满足给定特性阻抗参数的键合线长度。 提供了用于生成分割的边界参数，包括对相应半导体芯片的面积参数上的部分数量和可选地包含的界限。

公开(公告)号：US09000808B2

公开(公告)日：2015-04-07

申请号：US12790362

申请日：2010-05-28

申请人： Dominicus M. Roozeboom ,  Sharad Murari ,  Harold Garth Hanson

发明人： Dominicus M. Roozeboom ,  Sharad Murari ,  Harold Garth Hanson

IPC分类号： H03K5/153 ,  H03K19/173 ,  H03M1/36

CPC分类号： H03K19/017581 ,  H03K5/24 ,  H03K19/173 ,  H03M1/365

摘要： A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

摘要翻译： 状态检测电路有助于检测输入引脚相对于多种不同类型的输入电路的状态。 根据示例实施例，状态检测电路包括多个比较器和电路部件，其被配置为提供多个二进制输出信号，其共同指示比较器耦合到的输入引脚的状态。 状态检测电路被配置为便于基于二进制输出信号检测几种不同类型的输入电路。

公开(公告)号：US08482114B2

公开(公告)日：2013-07-09

申请号：US12757466

申请日：2010-04-09

申请人： James Raymond Spehar ,  Christian Paquet ,  Wayne A. Nunn ,  Dominicus M. Roozeboom ,  Joseph E. Schulze ,  Fatha Khalsa

发明人： James Raymond Spehar ,  Christian Paquet ,  Wayne A. Nunn ,  Dominicus M. Roozeboom ,  Joseph E. Schulze ,  Fatha Khalsa

IPC分类号： H01L23/48

CPC分类号： G06F17/5045 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/48011 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

摘要翻译： 高带宽电路被分割成多个部分，每个部分用于在对应的半导体芯片上实现，产生用于每个相应芯片的一个或多个管芯焊盘的布置，并且产生用于每个相应芯片的芯片位置，给定 产生封装和给定的封装I / O布置，芯片键合布置的产生和芯片位置相对于给定的芯片封装参数，并被产生以建立满足给定特性阻抗参数的键合线长度。 提供了用于生成分割的边界参数，包括对相应半导体芯片的面积参数上的部分数量和可选地包含的界限。

公开(公告)号：US20110291704A1

公开(公告)日：2011-12-01

申请号：US12790362

申请日：2010-05-28

申请人： Dominicus M. Roozeboom ,  Sharad Murari ,  Harold Garth Hanson

发明人： Dominicus M. Roozeboom ,  Sharad Murari ,  Harold Garth Hanson

IPC分类号： H03K5/22

CPC分类号： H03K19/017581 ,  H03K5/24 ,  H03K19/173 ,  H03M1/365

摘要： A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.

摘要翻译： 状态检测电路有助于检测输入引脚相对于多种不同类型的输入电路的状态。 根据示例实施例，状态检测电路包括多个比较器和电路部件，其被配置为提供多个二进制输出信号，其共同指示比较器耦合到的输入引脚的状态。 状态检测电路被配置为便于基于二进制输出信号检测几种不同类型的输入电路。

公开(公告)号：US06580292B2

公开(公告)日：2003-06-17

申请号：US09922420

申请日：2001-08-02

申请人： Jeffrey Alma West ,  Robert John Marshall ,  Alma Anderson ,  Dominicus M Roozeboom

发明人： Jeffrey Alma West ,  Robert John Marshall ,  Alma Anderson ,  Dominicus M Roozeboom

IPC分类号： H03K190175

CPC分类号： H03K19/018585

摘要： The invention implements a Positive Emitter Coupled Logic (PECL) output using CMOS transistors that approximate the Motorola ECL characteristics into standard PECL termination schemes. By creating a PECL output using a switchable current source the PECL output can be integrated into a Low Voltage Differential Signaling (LVDS) structure. The invention allows the user to switch between PECL and LVDS outputs via control logic by enabling the specific circuit elements for each signaling technology. With this invention, the combination of two drivers on one IC device gives system designers the flexibility to use the same circuitry in two separate signaling schemes. Thus, the designers can select to use one output characteristics or the other for their designs.

摘要翻译： 本发明使用CMOS晶体管实现了正发射极耦合逻辑（PECL）输出，其将摩托罗拉ECL特性近似为标准PECL端接方案。 通过使用可切换电流源创建PECL输出，PECL输出可以集成到低电压差分信号（LVDS）结构中。 本发明允许用户通过使每个信号技术的特定电路元件经由控制逻辑在PECL和LVDS输出之间切换。 利用本发明，一个IC器件上的两个驱动器的组合为系统设计人员提供了在两个单独的信令方案中使用相同电路的灵活性。 因此，设计师可以选择使用一种输出特性或另一种用于其设计。