发明申请
- 专利标题: PLL CIRCUIT WITH IMPROVED PHASE DIFFERENCE DETECTION
- 专利标题(中): 具有改进的相位差检测的PLL电路
-
申请号: US12952705申请日: 2010-11-23
-
公开(公告)号: US20110064150A1公开(公告)日: 2011-03-17
- 发明人: Toshiya UOZUMI , Keisuke UEDA , Mitsunori SAMATA , Satoru YAMAMOTO , Russell P. Mohn , Aleksander DEC , Ken SUYAMA
- 申请人: Toshiya UOZUMI , Keisuke UEDA , Mitsunori SAMATA , Satoru YAMAMOTO , Russell P. Mohn , Aleksander DEC , Ken SUYAMA
- 申请人地址: JP Kawasaki-shi
- 专利权人: RENESAS ELECTRONICS CORPORATION
- 当前专利权人: RENESAS ELECTRONICS CORPORATION
- 当前专利权人地址: JP Kawasaki-shi
- 主分类号: H04L27/00
- IPC分类号: H04L27/00 ; H03L7/085
摘要:
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
公开/授权文献
- US08754713B2 PLL circuit with improved phase difference detection 公开/授权日:2014-06-17
信息查询