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公开(公告)号：US08754713B2
公开(公告)日：2014-06-17
申请号：US12952705
申请日：2010-11-23
申请人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/00
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈回路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US20110064150A1
公开(公告)日：2011-03-17
申请号：US12952705
申请日：2010-11-23
申请人： Toshiya UOZUMI , Keisuke UEDA , Mitsunori SAMATA , Satoru YAMAMOTO , Russell P. Mohn , Aleksander DEC , Ken SUYAMA
发明人： Toshiya UOZUMI , Keisuke UEDA , Mitsunori SAMATA , Satoru YAMAMOTO , Russell P. Mohn , Aleksander DEC , Ken SUYAMA
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US07859344B2
公开(公告)日：2010-12-28
申请号：US12111458
申请日：2008-04-29
申请人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya Uozumi , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/00
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US20090267664A1
公开(公告)日：2009-10-29
申请号：US12111458
申请日：2008-04-29
申请人： Toshiya UOZUMI , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P. Mohn , Aleksander Dec , Ken Suyama
发明人： Toshiya UOZUMI , Keisuke Ueda , Mitsunori Samata , Satoru Yamamoto , Russell P. Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/06
摘要： In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
摘要翻译： 在由数字电路构成的ADPLL中，提供了在相位差0（零）附近改善相位差检测的技术。 反馈环路包括比较参考信号和反馈信号的相位和频率的PFD，将PFD的输出转换为数字值的TDC，从TDC的输出去除高频噪声分量的DLF，DCO控制 基于DLF的输出和DIV对DCO的输出进行分频并输出反馈信号。 在反馈回路的任何部分附加偏移值，即使ADPLL被锁定，反馈信号的相位被控制，并且除了0之外的值被输入到TDC。
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公开(公告)号：US20100097150A1
公开(公告)日：2010-04-22
申请号：US12252443
申请日：2008-10-16
申请人： Keisuke Ueda , Toshiya Uozumi , Satoru Yamamoto , Mitsunori Samata , Russell P. Mohn , Aleksander Dec , Ken Suyama
发明人： Keisuke Ueda , Toshiya Uozumi , Satoru Yamamoto , Mitsunori Samata , Russell P. Mohn , Aleksander Dec , Ken Suyama
IPC分类号： H03L7/08
CPC分类号： H03L7/1976 , H03L7/089 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.
摘要翻译： 提供一种用于抑制由于在PLL电路中对模拟电路进行数字化而产生的量化噪声的技术。 PLL电路包括：数字相位频率检测器，其检测（比较）参考信号的相位和频率以及分频信号，并将其转换为数字值; 数字环路滤波器，其从数字相位频率比较器的输出消除高频噪声分量; 数字模拟转换器，其将数字环路滤波器的输出的数字值转换为模拟值; 模拟滤波器，其从数字 - 模拟转换器的输出消除高频噪声分量; 基于模拟滤波器的输出来控制频率的压控振荡器; 以及分频器，其分压电压控制振荡器的频率并输出分频信号。
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