发明申请
- 专利标题： PHASE DETECTING CIRCUIT AND PLL CIRCUIT
- 专利标题（中）： 相位检测电路和PLL电路
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申请号： US12728120申请日： 2010-03-19
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公开(公告)号： US20110187413A1公开(公告)日： 2011-08-04
- 发明人: Atsushi Suzuki
- 申请人： Atsushi Suzuki
- 申请人地址： JP Tokyo
- 专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址： JP Tokyo
- 优先权： JP2010-023474 20100204
- 主分类号： H03D13/00
- IPC分类号： H03D13/00 ; H03L7/06
摘要：
A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an AND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states.
公开/授权文献
- US08138800B2 Phase detecting circuit and PLL circuit 公开/授权日：2012-03-20
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