发明申请
- 专利标题: METHOD OF MANUFACTURING LAYERED CHIP PACKAGE
- 专利标题(中): 制造分层芯片包装的方法
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申请号: US12700297申请日: 2010-02-04
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公开(公告)号: US20110189822A1公开(公告)日: 2011-08-04
- 发明人: Yoshitaka SASAKI , Hiroyuki ITO , Atsushi IIJIMA
- 申请人: Yoshitaka SASAKI , Hiroyuki ITO , Atsushi IIJIMA
- 申请人地址: US CA Milpitas CN Hong Kong
- 专利权人: HEADWAY TECHNOLOGIES, INC.,SAE MAGNETICS (H.K.) LTD.
- 当前专利权人: HEADWAY TECHNOLOGIES, INC.,SAE MAGNETICS (H.K.) LTD.
- 当前专利权人地址: US CA Milpitas CN Hong Kong
- 主分类号: H01L21/78
- IPC分类号: H01L21/78
摘要:
A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.
公开/授权文献
- US08298862B2 Method of manufacturing layered chip package 公开/授权日:2012-10-30
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