公开(公告)号：US20130176644A1

公开(公告)日：2013-07-11

申请号：US13344081

申请日：2012-01-05

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hironori ARAKI ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hironori ARAKI ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/17 ,  G11B5/127 ,  G11B5/48

CPC分类号： G11B5/1278 ,  G11B5/3116 ,  G11B5/3163 ,  Y10T29/49021

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, a thin-film coil and a shield magnetic layer are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. This thin-film magnetic head has a hard guard frame layer surrounding an equidistant coil part, disposed at a position equidistant from the substrate, from outside and being in direct contact with almost a whole outside surface defining an outer shape of the equidistant coil part.

摘要翻译： 薄膜磁头被构造成使得主磁极层，写入屏蔽层，间隙层，薄膜线圈和屏蔽磁性层被层压在基板上。 薄膜磁头具有屏蔽磁性层。 该薄膜磁头具有围绕等离子体线圈部分的等距线圈部分的硬保护框架层，其设置在距离基板等距离的位置，并且与限定等距线圈部分的外部形状的几乎整个外表面直接接触。

公开(公告)号：US20120257304A1

公开(公告)日：2012-10-11

申请号：US13084168

申请日：2011-04-11

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/10

CPC分类号： G11B5/315 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/314 ,  G11B5/607

摘要： A magnetic head includes a coil, a main pole, a write shield, and first and second yoke layers. The first and second yoke layers are magnetically connected to the write shield and aligned along the direction of travel of a recording medium such that the main pole is interposed therebetween. The coil includes a winding portion of planar spiral shape that is formed in one or more layers. The magnetic head further includes: a first coupling part located away from the medium facing surface and magnetically coupling the main pole and the second yoke layer to each other; and a second coupling part located away from the medium facing surface and magnetically coupling the first yoke layer and the second yoke layer to each other without touching the main pole. The winding portion is wound around the first coupling part, and a part of the winding portion passes between the first and second coupling parts.

摘要翻译： 磁头包括线圈，主极，写入屏蔽以及第一和第二磁轭层。 第一和第二磁轭层磁性地连接到写入屏蔽并沿着记录介质的行进方向对准，使得主极插入其间。 线圈包括形成为一层或多层的平面螺旋形状的绕组部分。 磁头还包括：第一耦合部件，其远离介质面对表面并将主极和第二磁轭层彼此磁耦合; 以及第二耦合部件，其远离所述介质面对表面并且将所述第一磁轭层和所述第二磁轭层磁耦合到彼此而不接触所述主极。 卷绕部缠绕在第一连接部上，卷绕部的一部分在第一和第二连接部之间通过。

公开(公告)号：US20120170156A1

公开(公告)日：2012-07-05

申请号：US12982349

申请日：2010-12-30

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/127

CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3146

摘要： A magnetic head includes: a coil; a main pole; a first shield disposed backward of the main pole along a direction of travel of a recording medium; a first return path section connecting the first shield to the main pole; a second shield disposed forward of the main pole along the direction of travel of the recording medium; and a second return path section connecting the second shield to the main pole. An interface between the first return path section and the main pole has an end closest to a medium facing surface, and an interface between the second return path section and the main pole has an end closest to the medium facing surface, the latter being closer to the medium facing surface than the former. The second return path section includes a yoke layer located away from the medium facing surface and in contact with the main pole. The coil includes at least one coil element that passes between the second shield and the yoke layer.

摘要翻译： 磁头包括：线圈; 主杆 第一屏蔽件，沿着记录介质的行进方向设置在所述主极的后方; 将第一屏蔽件连接到主极的第一返回路径部分; 第二屏蔽件，其沿着记录介质的行进方向设置在主极的前方; 以及将第二屏蔽件连接到主极的第二返回路径部分。 第一返回路径部分和主极之间的界面具有最靠近介质面的表面的端部，并且第二返回路径部分和主极之间的界面具有最靠近介质面向表面的一端，后者更靠近 中等面向表面比前者。 第二返回路径部分包括位于远离介质面向表面并与主极接触的磁轭层。 线圈包括在第二屏蔽和轭层之间通过的至少一个线圈元件。

公开(公告)号：US20120086130A1

公开(公告)日：2012-04-12

申请号：US12902600

申请日：2010-10-12

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/92 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0362 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05552

摘要： A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体。 主体包括主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 主要部分包括第一和第二层部分，以及贯穿它们的电极。 通孔电连接到第一和第二端子。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且还包括表面电极。 表面电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 第一端子通过使用第一层部分的表面电极形成。 第二端子通过使用第二层部分的表面电极形成。

公开(公告)号：US20130100555A1

公开(公告)日：2013-04-25

申请号：US13279978

申请日：2011-10-24

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/31 ,  G11B5/127 ,  G11B5/48

CPC分类号： G11B5/1278 ,  G11B5/3116 ,  G11B5/315 ,  G11B5/3163 ,  Y10T29/49023 ,  Y10T29/49032 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a lower shield layer, an upper shield layer and a thin-film coil are laminated on a substrate. A method of manufacturing the thin-film magnetic head has a lower shield layer forming step. This step comprises a step of forming a first lower shield part in a lower shield planned area, including a planned line along the medium-opposing surface, a step of forming a partial lower seed layer having a partial arrangement structure in which the partial lower seed layer is arranged on a lower formation zone except a lower exception zone including the planned line, a step of forming a second lower shield part on the partial lower seed layer.

摘要翻译： 薄膜磁头被构造成使得主磁极层，下屏蔽层，上屏蔽层和薄膜线圈层叠在基板上。 制造薄膜磁头的方法具有较低的屏蔽层形成步骤。 该步骤包括在下屏蔽计划区域中形成第一下屏蔽部分的步骤，包括沿着中间相对表面的计划线，形成具有部分布置结构的部分下部种子层的步骤，其中部分下部种子 层布置在下形成区域，除了包括预定线的下异常区域，在部分下种子层上形成第二下屏蔽部分的步骤。

公开(公告)号：US20130020723A1

公开(公告)日：2013-01-24

申请号：US13184971

申请日：2011-07-18

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/52

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/27 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.

摘要翻译： 复合分层芯片封装包括彼此堆叠的多个子封装。 每个子包包括主体和接线。 主体包括包括多个层部分的主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 布线电连接到第一和第二端子。 包括在主要部分中的多个层部分的数量对于所有多个子包是相同的，并且每个子包中的多个层部分包括至少一个第一类型层部分。 在至少两个子包中的每一个中，多个层部分还包括至少一个第二类型层部分。 第一型层部分包括连接到布线的半导体芯片，而第二型层部分包括未连接到布线的半导体芯片。

公开(公告)号：US20120256321A1

公开(公告)日：2012-10-11

申请号：US13084053

申请日：2011-04-11

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括：电连接到多个公共线的多个公共电极; 多个非接触电极，其电连接到与层相关的线，并且不与层部分中的半导体芯片接触; 以及选择性连接电极，其仅选择性地电连接到所述层部分在多个层相关线中使用的与层相关的线。 层相关线大于最大宽度的公共线。

公开(公告)号：US20120025355A1

公开(公告)日：2012-02-02

申请号：US12848595

申请日：2010-08-02

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/544 ,  H01L21/00 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件。 此外，最上面的基板和最下面的基板在使用铁磁体的划线槽部以外的区域中形成有电磁屏蔽层。 此外，在层叠半导体基板中，在划线槽部形成有贯穿层叠方向的多个半导体基板的贯通孔，并且层叠半导体基板具有穿过多个半导体基板的通孔， 孔。

公开(公告)号：US20110189822A1

公开(公告)日：2011-08-04

申请号：US12700297

申请日：2010-02-04

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L2224/16

摘要： A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括堆叠的多个层部分。 布线布置在主体的至少一个侧表面上。 在制造层状芯片封装的方法中，首先，使用多个子结构，每个子结构包括多个预备层部分的阵列，以制造包括排成行的多个预分离主体的分层子结构。 接下来，将分层子结构切割成多个块，每个块包括一行多个预分离主体，并且布线同时形成在包括在每个块中的多个预分离主体上。 然后将多个预分离主体彼此分离。 多个块中的每个块包括一行三个，四个或五个预分离主体。

公开(公告)号：US20130308227A1

公开(公告)日：2013-11-21

申请号：US13473159

申请日：2012-05-16

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Yukinori IKEGAWA ,  Atsushi IIJIMA ,  Tatsuya SHIMIZU

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Yukinori IKEGAWA ,  Atsushi IIJIMA ,  Tatsuya SHIMIZU

IPC分类号： G11B5/17 ,  G11B5/127

CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3123 ,  G11B5/315 ,  G11B5/3163

摘要： A magnetic head includes a magnetic structure incorporating a write shield. The magnetic structure is formed to include a first magnetic layer, a second magnetic layer stacked on the first magnetic layer, and a seed layer. The first magnetic layer has a front end face located in the medium facing surface and a top surface. The second magnetic layer has a front end face located in the medium facing surface and a bottom surface. The top surface of the first magnetic layer includes a first region including an end located in the medium facing surface and a second region farther from the medium facing surface than the first region. The seed layer is not present on the first region of the top surface of the first magnetic layer but is present on the second region.

摘要翻译： 磁头包括结合有写入屏蔽的磁性结构。 磁结构形成为包括第一磁性层，堆叠在第一磁性层上的第二磁性层和种子层。 第一磁性层具有位于介质相对表面中的前端面和顶面。 第二磁性层具有位于介质面向表面中的前端面和底面。 第一磁性层的顶表面包括第一区域和第二区域，第一区域包括位于介质面向表面中的端部和比介质面向表面比第一区域更远的第二区域。 种子层不存在于第一磁性层的顶表面的第一区域上，但存在于第二区域上。