Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage. The first power supply voltage is a first reference voltage, which is a most spaced from the second voltage section among the first reference voltage group, or a predetermined voltage even further spaced from the second voltage section than the first reference voltage. The second power supply voltage is a predetermined voltage within a range from a second reference voltage, which is a voltage closest to the first voltage section among the second reference voltage group, to a voltage within the first voltage section but not reaching the first reference voltage.