公开(公告)号：US08446403B2

公开(公告)日：2013-05-21

申请号：US13027450

申请日：2011-02-15

申请人： Hiroshi Tsuchi ,  Nobuyasu Doi

发明人： Hiroshi Tsuchi ,  Nobuyasu Doi

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3283 ,  G09G3/3291 ,  G09G2310/027

摘要： Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

摘要翻译： 公开了一种解码器，接收第一和第二参考电压组并根据接收到的数字信号选择参考电压，包括接收第一参考电压组的第一子解码器，接收第二参考电压的第二子解码器 并且第三子解码器接收由第二子解码器选择的参考电压，并将所选择的参考电压输出到解码器的第一子解码器或输出端。 第一子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管，第二子解码器包括具有提供有第二电源电压的背栅的第一导电类型的晶体管， 并且第三子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管。

公开(公告)号：US20110205218A1

公开(公告)日：2011-08-25

申请号：US13027450

申请日：2011-02-15

申请人： Hiroshi TSUCHI ,  Nobuyasu Doi

发明人： Hiroshi TSUCHI ,  Nobuyasu Doi

IPC分类号： G09G5/00 ,  H03K5/22

CPC分类号： G09G3/3688 ,  G09G3/3283 ,  G09G3/3291 ,  G09G2310/027

摘要： Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage. The first power supply voltage is a first reference voltage, which is a most spaced from the second voltage section among the first reference voltage group, or a predetermined voltage even further spaced from the second voltage section than the first reference voltage. The second power supply voltage is a predetermined voltage within a range from a second reference voltage, which is a voltage closest to the first voltage section among the second reference voltage group, to a voltage within the first voltage section but not reaching the first reference voltage.

摘要翻译： 公开了一种解码器，接收第一和第二参考电压组并根据接收到的数字信号选择参考电压，包括接收第一参考电压组的第一子解码器，接收第二参考电压的第二子解码器 并且第三子解码器接收由第二子解码器选择的参考电压，并将所选择的参考电压输出到解码器的第一子解码器或输出端。 第一子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管，第二子解码器包括具有提供有第二电源电压的背栅的第一导电类型的晶体管， 并且第三子解码器包括具有提供有第一电源电压的背栅的第一导电类型的晶体管。 第一电源电压是与第一参考电压组中的第二电压部分最多隔开的第一参考电压或者与第二电压部分比第一参考电压更远的预定电压。 第二电源电压是从第二参考电压组中最接近第一电压部分的电压的第二参考电压到第一电压部分内的电压但没有达到第一参考电压的范围内的预定电压 。

公开(公告)号：US20080136805A1

公开(公告)日：2008-06-12

申请号：US11987997

申请日：2007-12-06

申请人： Hirokazu Kawagoshi ,  Nobuyasu Doi

发明人： Hirokazu Kawagoshi ,  Nobuyasu Doi

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G2330/02

摘要： A display panel drive apparatus is provided with: a drive circuit outputting drive voltages to a display panel in response to a timing control signal used for timing control of image display on the display panel; and a booster circuit feeding a boosted power supply voltage to the drive circuit. The booster circuit includes a charge pump circuit generating the boosted power supply voltage by boosting an input power supply voltage in response to a boosting clock; and a pulse skip circuit monitoring a voltage level of the boosted power supply voltage and controlling an boosting operation of the charge pump circuit in response to the voltage level of the boosted power supply voltage. The pulse skip circuit is configured to allow the charge pump circuit to initiate the boosting operation in synchronization with the timing control signal.

摘要翻译： 显示面板驱动装置具有：响应用于显示面板上的图像显示的定时控制的定时控制信号，向驱动电路输出驱动电压的驱动电路; 以及将升压的电源电压馈送到驱动电路的升压电路。 升压电路包括电荷泵电路，其通过响应于升压时钟升高输入电源电压而产生升压的电源电压; 以及脉冲跳过电路，其监视升压的电源电压的电压电平，并且响应于升压的电源电压的电压电平来控制电荷泵电路的升压操作。 脉冲跳跃电路被配置为允许电荷泵电路与定时控制信号同步地启动升压操作。

公开(公告)号：US08373695B2

公开(公告)日：2013-02-12

申请号：US11987997

申请日：2007-12-06

申请人： Hirokazu Kawagoshi ,  Nobuyasu Doi

发明人： Hirokazu Kawagoshi ,  Nobuyasu Doi

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G2330/02

摘要： A display panel drive apparatus is provided with: a drive circuit outputting drive voltages to a display panel in response to a timing control signal used for timing control of image display on the display panel; and a booster circuit feeding a boosted power supply voltage to the drive circuit. The booster circuit includes a charge pump circuit generating the boosted power supply voltage by boosting an input power supply voltage in response to a boosting clock; and a pulse skip circuit monitoring a voltage level of the boosted power supply voltage and controlling an boosting operation of the charge pump circuit in response to the voltage level of the boosted power supply voltage. The pulse skip circuit is configured to allow the charge pump circuit to initiate the boosting operation in synchronization with the timing control signal.

摘要翻译： 显示面板驱动装置具有：响应用于显示面板上的图像显示的定时控制的定时控制信号，向驱动电路输出驱动电压的驱动电路; 以及将升压的电源电压馈送到驱动电路的升压电路。 升压电路包括电荷泵电路，其通过响应于升压时钟升高输入电源电压而产生升压的电源电压; 以及脉冲跳过电路，其监视升压的电源电压的电压电平，并且响应于升压的电源电压的电压电平来控制电荷泵电路的升压操作。 脉冲跳跃电路被配置为允许电荷泵电路与定时控制信号同步地启动升压操作。

公开(公告)号：US06577318B1

公开(公告)日：2003-06-10

申请号：US09469195

申请日：1999-12-21

申请人： Nobuyasu Doi

发明人： Nobuyasu Doi

IPC分类号： G06T1100

CPC分类号： G11C7/1051 ,  G09G3/06 ,  G11C2207/107

摘要： An integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the data indicating the order of reading the parallel data from the first memory unit and the order of converting the parallel data into the serial data.

摘要翻译： 集成电路装置包括第一存储器单元和用于将从第一存储器单元读取的并行数据转换成串行数据的转换部件。 集成电路装置还包括第二存储器单元，其可以写入和读取指示从第一存储器单元读取并行数据的顺序的数据以及将并行数据转换为串行数据的顺序。