A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.